Dual Counter-Timer. CDP1878C Datasheet

CDP1878C Counter-Timer. Datasheet pdf. Equivalent


GE CDP1878C
CMOS Peripherals
CDP1878, CDP1878C
TNT
TAO
TAO
TAG
TACL
Rii
X-OIMEM
TPBiWR
TPA
CS
AO
AI
A2
VSS
3
4
7
8
9
10
II
12
13
14
TOP
28 VDD
27 DB7
26 DB6
25 DBS
24 DB4
23 DB3
22 OB2
21 OBI
20 DBO
19 TBO
18 TIll
17 TBG
16 TBCL
IS mET
VIEW
92CS-34626
TERMINAL ASSIGNMENT
CMOS Dual Counter-Timer
Features:
• Compatible with general-purpose and CDP1BOO-series
microprocessor systems
• Two 16-bit down-counters and two B-bit control registers
• 5 modes including a versatile variable-duty cycle mode
• Programmable gate-level select
• Two-complemented output pins for each counter-timer
• Software-controlled interrupt output
• Addressable in memory space or CDP1BOO-series I/O space
The RCA-CDP1878 and CDP1878C8 are dual counter-
timers consisting of two 16-bit programmable down
counters that are independently controlled by separate
control registers. The value in the registers determine the
mode of operation and control functions. Counters and
registers are directly addressable in memory space by any
general-industry-type microprocessors, in addition to
input/output mapping with the CDP1800-series micropro-
cessors.
Each counter-timer can be configured in five' modes with
the additional flexibility of gate-level control. The control
registers in addition to mode formatting, allow software
start and stop, interrupt enable, and an optional read
control that allows a stable readout from the counters. Each
counter-timer has software control of a common interrupt
output with an interrupt status register Indicating which
counter-timer has timed out.
In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.
The CDP1878 and CDP1878C are functionally identical.
They differ in that the CDP1878 has a recommended
operating voltage range of 4 to 10.5 volts, and the
CDP1878C has a recommended operating voltage range of
4 to 6.5 volts. These types are supplied in 28-lead dual-in-
line ceramic packages (0 suffix), and 28-lead dual-in-line
plastic packages (E suffix).
toFormerly RCA Dev. Type No. TA1098l and TA10981C, respectivel'
4
Table I - Mode Description
Mode
Function
1 Timeout
Outouts chance when clock decrements counter to "0"
2 Timeout Strobe
One clockwide output pulse when clock decrements
counJer to "0"
3 Gate-Controlled One Shot Outputs c,hange when clock decrements counter to "0".
Retriggerable
4 Rate Generator
Reoetitive clockwide outout oulse
5 Variable-Duty Cycle
Repetitive output with programmed duty cycle
Application
Event counter
Trigger pulse
Time-delay generation
Time-base....9.enerator
Motor control
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum reliability.
operating condition. should be selected 10 that operation II alwaYI within the following range.:
CHARACTERISTIC
DC Operating Voltage 8ange
Input Voltage Range
Maximum Clock Input Rise or
Fall Time
tr,tf
Minimum Clock Pulse Width
tWL, tWH
Maximum Clock Input Frequency,
fCl
LIMITS
CDP1878
Min. Max.
4 10.5
V!,:!,: VDD
CDP1878C
Min. Max,
4 6.5
Vss VjID
- 5- 5
200 200
DC 1 DC 1
UNITS
V
ps
ns
MHz
File Number 1341
_______________________________________________________________ 439


CDP1878C Datasheet
Recommendation CDP1878C Datasheet
Part CDP1878C
Description CMOS Dual Counter-Timer
Feature CDP1878C; CMOS Peripherals CDP1878, CDP1878C TNT TAO TAO TAG TACL Rii X-OIMEM TPBiWR TPA CS AO AI A2 VSS 3 4.
Manufacture GE
Datasheet
Download CDP1878C Datasheet




GE CDP1878C
CMOS Peripherals
CDP1878, CDP1878C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS terminal)
CDPI878 ..........................................................................................................-0.5 to +11 V
CDP1878C ........................................................................................................-0 5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ........................................................................ -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (PO)·
For TA=-40 to +60° C (PACKAGE TYPE E) ............. , ................................................................. 500 mW
For TA=+60 to +85° C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/oC to 200 mW
For TA=-S5 to +100°C (PACKAGE TYPE D) ............................................................................. 500 mW
For TA=+100 to 125°C (PACKAGE TYPE D) ............................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA).
PACKAGE TYPE D............................................................................................... -55 to +125°C
PACKAGE TYPE E ................................................................................................ -40 to +85°-C
STORAGE-TEMPERATURE RANGE (Tstg) .......................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING).
At distance 1/16 ± 1/32 In. (1 59 ± 0.79 mm) from case for 10 s max ..................................................... +265"C
STATIC ELECTRICAL CHARACTJ;RISTICS at TA=-40 to +8S"C, VOO ±S%, Except as noted
CHARACTERISTIC
CONDITIONS
Vo VIN VOO
(V) (V) (V)
QUiescent Device Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High Level
Input Low Voltage
Input High Voltage
Input Leakage Current
Operating Current
Input Capacitance
Output Capacitance
-
IDD -
0.4
IOL 0.5
4.6
IOH 9.5
-
VOL:j: -
-
VOH:j: -
0.5,4.5
VIL
0.5,9.5
0.5,4.5
VIH 0.5,9.5
Any
liN Input
-
IDD1A -
CIN -
COUT -
0, 5
0, 10
0,5
0, 10
0, 5
0, 10
0,5
0, 10
0, 5
0, 10
-
-
-
-
0,5
0, 10
0, 5
o 10
-
-
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
LIMITS
COP1878
COP1878C
Min. Typ.- Max. Min. Typ.- Max..
- 0.01 50 - 0.02 200
-
-1 200
-
-
1.6 3.2
-
-1.6 3.2
2.6 5.2
-
-
-
-
-1.15 -2.3
-
-1.15 -2.3
-
-2.6 -5.2
-0
-0
-
0.1
0.1
-
-
-
--
0 0.1
--
4.9 5 -
4.9 5 -
9.9 10 - - - -
- - 1.5 - - 1.5
--
3-
--
3.5 - - 3.5 - -
7- - - - -
- - ±1 - - ±1
- - ±2 - - -
-- 1.5 3
1.5 3
-
6 12 -
-
-
- 5 7.5 - 5 7.5
- 10 15 - 10 15
UNITS
pA
rnA
V
pA
rnA
pF
"Typical values are for TA=25" C and nominal VDD
*IOL=IOH=II'A.
t.Operating current is measured at 200 kHz for VDD=5 Vand 400 kHz for VDD=10 V, with open outputs (worst-case frequencies for
CDP1802A system operating at maximum speed of 3.2 MHz)
440 _________________________________________________________________



GE CDP1878C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP1878, CDP1878C
RESET
lfIj
TPB/YiR
I-o/iifil
TPA
CS
A2
AI
AO
I-O
CONTROL
AND
LOGIC
8-81T
EXTERNAL
BUS
DATA
BUS
DRIVERS
GATE A
INT AND
STATUS REGISTER
GATE B
.-------L-"1-.. T80
m
CLOCK B
III
Fig. 1 - Functional diagram CDP1878 and CDP1878C.
92CL-34627
FunctIonal Oellnltlonllor COP1878 and COP1878C Termlnall
TERMINAL
USAGE
VDD-VSS Power
DBO-DB7 Data to and from device
TPB/wrI, J!rn Directional control signals
AO, A1, A2 Addresses that select counters
or registers
TACL, TBCL Clocks used to decrement counters
TAG, TBG Gate inputs that control counters
TAO,TAO Complemented outputs of Timer A
TBO, i'BO Complemented outputs of Timer B
TPA
Used with CDP1800-series processors,
tied high otherwise
TERMINAL
CS
'1m'
Rffii'
I-O/MEM
USAGE
Active high input that enables device
Low when counter is "0"
rnaWhen active, TAO, TBO are low,
TAb,
are high. Interrupt status
register is cleared
Tied high in CDP1800 input/output
mode, otherwise tied low
____________________________________________________________
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