Asynchronous Receiver/Transmitter. CDP6402 Datasheet

CDP6402 Receiver/Transmitter. Datasheet pdf. Equivalent


GE CDP6402
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP6402, CDP6402C
VDD TRC
NC 'PE
GND CLSI
RRD -
RBRe
CLS2
S8S
RBR7
PI
RBR6
CRL
RBR5
T8RS
RBR4
TBRl
RSR3
TeR6
ReR2
T8R5
RBR'
TBR4
PE TeR 3
FE TBR2
DE T8Rl
SFD TRO
RRC
~
TRE
TBRl
OR
RRI
TBRE
MR
TOP VIEW
92CS-34552
TERMINAL ASSIGNMENT
CMOS Universal Asynchronous
Receiver/Transmitter (UART)
Features:
• Low-power CMOS circuitry -
7.5 mW typo at 3.2 MHz
• Fully programmable with externally
selectable word length (5-8 bits),
(max. freq.) at VDD = 5 V
parity inhibit, even/odd parity, and
• Baud rate - DC to 200K bits/sec (max.)
I, 1.5,or 2 stop bits
at VDD = 5 V, 85°C
• Operating-temperature range:
DC to 400K bits/sec (max.)
(CDP6402D, CD) -55 to +125°
at VDD = 10 V,85°C
(CDP6402E, CE) -40 to +85° C
• 4 V to 10.5 operation
• AutomatIc data formatting and
• Replaces industry types IM6402
and HD6402
status generation
The RCA CDP6402 and CDP6402C are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART)
circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to
provide the necessary formatting and control for interfacing
between serial and parallel data channels. The receiver
converts serial start, data, parity, and stop bits to parallel
TRE +-r--------,
data verifying proper code transmission, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start parity and stop bits.
The data word can be 5, 6, 7 or 8 bits in length. Parity may be
odd, even or inhibited. Stop bits can be 1, 1.5, or 2 (when
transmitting 5-bit code).
III
TRC
L---------------j-+TRO
ClSI-~--+_-----+_--------~--~~--~----------------------------------------------_t-SBS
CLS2
EPE
CRL--r---t---------t---------~_ __.----~----------------------------------------------_t-Pl
MR
,-----------------------------------------~_+--4__RRI
SFD
DR OE TBRE
FE PE RBRe (MSBI
Fig. 1 - Functional block diagram.
~----------.;__ RRD
RBRI (LSB) 92CL-34553
File Number 1328
479


CDP6402 Datasheet
Recommendation CDP6402 Datasheet
Part CDP6402
Description CMOS Universal Asynchronous Receiver/Transmitter
Feature CDP6402; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals CDP6402, CDP6402C VDD TRC NC.
Manufacture GE
Datasheet
Download CDP6402 Datasheet




GE CDP6402
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..;.;;....
CDP6402, CDP6402C
The CDP6402 and CDP6402C can be used in a wide range
of applications including modems, printers, peripherals,
video terminals, remote data acquisition systems, and serial
data links for distributed processing systems.
The CDP6402 and CDP6402C are functionally identical.
They differ in that the CDP6402 has a recommended
operating voltage range of 4 to 10.5 volts, and the CDP6402C
has a recommended operating voltage range of 4 to 6.5
volts. Both types are supplied in 40-lead dual-in-line ceramic
packages (0 suffix), and 40-lead dual-in-line plastic
packages (E suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS Terminal)
CDP6402 .......................................................................................-0.5to+11 V
CDP6402C .. '" ...........................................................••••.••.••..•.......••• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................ -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................. ± 100pA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60°C (PACKAGE TYPE E .............................................................. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................... Derate Lineary at 12 mW/oC to 200 mW
For TA = -55 to 100°C (PACKAGE TYPE D) ............................................................. 500 mW
For TA = + 100 to +125°C (PACKAGE TYPE D) ............................ Derate Lineary at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ....................••••..••..••• 100 mW
OPERATING-TEMPERATURE RANGE (TA).
PACKAGE TYPE 0 .............................................................................. -55 to +125°C
PACKAGE TYPE E ...................................................••.••.....•..................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg)' ......................................................... -85 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0 79 mm) from case for 10 s max..................................... +265°C
OPERATING CONDITIONS at TA = Full Package-Temperatura Range. For maximum reliability, operating condlUonl
Ihould be lelectad 80 that operation II alwaYI within the following rangel:
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
LIMITS
CDP6402
CDP6402C
Min.
Max.
Min.
Max.
4 10.5 4
6.5
VSS VDD VSS VDD
UNITS
V
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VDD ±100f0, Except al noted
CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
_'-Sink) Current
Output High Drive
(Source) Current
uutput Voltage
Low-Level
output voltage
High Level
Input Low
Voltage
Input Mlgn
Voltage
Input Leakage
Current
3-State Output Leakage
Current
Operating Current,
Input CapaCitance
Output Capacitance
IDD
IOL
IOH
VOLt
VOHt
Vil
VI~
liN
lOUT
IDD1t
CIN
COUT
CONDITIONS
~~ ~~ ~~r
0,5 5
- 0, 10 10
0.4
0.5
0°'150
150
4.6 0,5
5
9.5 0, 10 10
-
-
0.5,4.5
0.5,9.5
U.:>, 4.:>
0.5 9.5
Any
Input
0,5
0, 10
0,5
0, 10
--
-
0,5
o 10
5
10
150
5
10
:>
10
5
10
0,5 0,5
5
0, 10 0, 10 10
~'100 150
---
LIMITS
CDP6402
CDP6402C
Min. Typ.- Max. Min. TVD.· Max.
- - - -0.01 50
1 200
0.02 200
2
5
4
7
-
1.<!
-
2-.4
-
- - - --0.55 -1.1
-1.3 -2.6
-0.55 -1.1
- - - -0 0.1
0 0.1
U U.l
-4.9
9.9
150
4.9 5
--
-
-
- P.~ifoD -
-
o.s
-
-VDD-2
7
- -WDD-2 -
-
- - - -±1o-" ±1
±10-4 ±2
±1
- - - -±1O-" ±1
±10-4 ±10
±1O-" ±1
1.0 1.0
10
- -5 7.5
5 7.5
10 15
10 15
UNITS
pA
mA
V
pA
mA
pF
-Typical values are for TA=25°C and nominal VDD.
tlOL=IOW 1pA.
#Operating current is measured at 200 kHz or VDD = 5 V and 400 kHz for VDD = 10 V, with open outputs (worst-cal.
frequencies for CDP1802A system operating at maximum speed of 3.2 MHz).
480 ________________--------------------------------------



GE CDP6402
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP6402, CDP6402C
DESCRIPTION OF OPERATION
Receiver Operation
Initialization and Controls
Data is received in serial form at the RRI input. When no
data is being received, RRI input must remain high. The
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets
data is clocked through the RRC. The clock rate is 16 times
the data rate. Receiver timing is shown in Fig. 4.
the serial output (TRO) High. Timing is generated from the
clock inputs RRC and TRC at a frequency equal to 16 times
the serial data bit rate. The RRC and TRC inputs may be
driven by a common clock, or may be driven independently
by two different clocks. The CONTROL REGISTER lOAD
BEGINNING OF FiRST STOP BIT
~
"
_ , 8 1C1LO2CKTOCY9C1L1E2S
IRR I
DATA
Il
(CRl) input is strobed to load control bits for PARITY
INHIBIT (PI), EVEN pARITY ENABLE (EPE), STOP BIT
RBRI-B,OE
SELECTS (SBS), and CHARACTER lENGTH SELECTS
(ClS1 and ClS2). These inputs may be hand wired to VSS
or VDD with CRl to VDD. When the initialization is
completed, the UART is ready for receiver and/or transmitter
operations.
Transmitter Operation
The transmitter section accepts parallel data, formats it,
DR
FE ,PE
~~
I
A
-- ~ 112CLOCK
C CYCL E
and transmits it in serial form (Fig. 2) on the TRO terminal.
9ZCS -:!4ee'R2
STARTB""\ ,.
5-8 DATA BITS
I
1,1-1/20R2STOPBITS
1~
IL... ~x=LLL I I I'...J...ILS-B-.JIL......L--.JL......L-...JL......L--.JIL...-MSB...I...
Fig. 4 - Receiver timing waveforms.
(A) A low level on DRR clears the DR line. (B) During the
first stop bit data is transferred from the receiver register to
the RBRegister. If the word IS less than 8 bitS, the unused
~
*!F ENABLED
PARITY most significant bits will be a logic low. The output
92C5-34554
character is right justified to the least significant bit RBR1. A
logic high on OE indicates overruns. An overrun occurs
Fig. 2 - Serial data format.
when DR has not been cleared before the present character
was transferred to the RBR. (C) 1/2 clock cycle later DR is
Transmittertiming is shown in Fig. 3. (A) Data is loaded into
the transmitter buffer register from the inputs TBR1 through
TBR8 by a logic low on the TBRl input. Valid data must be
set to a logic high and FE is evaluated. A logic high on FE
indicates an invalid stop bit was received A logic high on
PE indicates a parity error.
present at least tDT prior to, and tTD following, the rising
edge of "i'trnI. If words less than 8 bits are used, only the
Start Bit Detection
least significant bits are used. The character is right
justified into the least significant bit, TBR1. (B) The rising
edge of TBRl clears TBRE. V, to 1'h cycles later, depending
on when the TBRl pulse occurs with respect to TRC, data is
transferred to the transmitter register and TRE is cleared.
TBRE is set to a logic High one cycle after that.
The receiver uses a 16X clock for timing (Fig. 5) The start
bit could have occurred as much as one clock cycle before it
was detected, as indicated by the shaded portion. The
center of the start bit is defined as clock count 7 1/2. If the
receiver clock is a symmetrical square wave, the center of
the start bit will be located within ±1/2 clock cycle, ±1/32 bit
Output data is clocked by TRC. The clock rate is 16 times
the data rate. (C) A second pulse on TBRl loads data into
or ±3.125%. The receiver begins searching for the next start
bit at 9 clocks into the first stop bit.
the transmitter buffer register Data transfer to the
transmitter register is delayed until transmission of the
current character is complete. (D) Data is automatically
transferred to the transmitter register and transmission of
that character begins.
CLOCK
COUNT 7 1/2
DEFINED CENTER
OF START BIT
RRI INPur----rn
START
!.. 1I..4--7C1YCL1ES 2CLOC~
8 1/2 CLOC K
CYCLES
92C$- 34558
Fig. 5 - Start bit timing waveforms.
92CS-3B054Rt
Fig. 3 - Transmitter timing waveforms.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 481







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