Static RAMs. CDP68HC68R1 Datasheet

CDP68HC68R1 RAMs. Datasheet pdf. Equivalent


GE CDP68HC68R1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
Product Preview
M~~~O:I :O:SI
NC 3
VSS 4
VIEWTOP
6 CE
5 ss
92CS-3786!5
TERMINAL ASSIGNMENT
CDP68HC68R1, CDP68HC68R2
CMOS 128-Word (CDP68HC68R1) and
256-Word (CDP68HC68R2) by
8-Bit Static RAMs
Features:
• Fully static operation
• Operating voltage range:
3 VtoS.S V
• Typical standby current=1 pA
• Directly compatible with
RCA/Motorola SPI bus
• Separate data input and three-
state data output pins
• Input data and clock buffers
gated off with chip enable
• Automatic sequencing for fast
multiple-byte accesses
• Low minimum data retention
voltage: 2 V
• Wide operating temperature
range: -40· C to +8S· C
The RCA CDP68HC68R1 and CDP68HC68R2are 128-word
and 256-word by 8-bit static random-access memories,
respectively. The memories are intended for use in systems
utilizing a synchronous serial three-wire (clock, data in, and
data out) interface where minimum package size,
interconnect wiring, low power, and simplicity of use are
desirable. These parts will interface directly with RCA's
CDP68HC05D2, CDP68HC05C4, and CDP68HC05C8
microcomputers (providing the CPHA bit in the
microcomputer's SPI Control Register is set equal to 1). The
CDP68HC68R1 and CDP68HC68R2 are also compatible
with general-purpose microcomputers, including RCA's
CDP1804A and CDP6805 family, by utilizing I/O bits forthe
SPI (Serial Peripheral Interface) bus. Other industry
microcomputers such as the 80C51 can also interface to
these serial RAM's.
The CDP68HC68R1 and CDP68HC68R2 are supplied in
8-lead plastic Mini-DIP packages (E suffix).
TRUTH TABLE
MODE
DISABLED
& RESET
READ
OR
WRITE
SHIFT
CE
L
X
H
H
SIGNAL
B
SCK
MOSI
MISO
X
INPUT
INPUT
H
DISABLED
DISABLED
HIGHZ
CPOL=O,
' -L
-.rCPOL=1,
DATA BIT
LATCH
HIGHZ
DURING WRITE,
CURRENT DATA BIT
DURING READ
fCPOL=O,
L
' - -CPOL=1,
X NEXT DATA
BIT
NOTE:
MISO remains at a High Z until8 bits of data are ready to be shifted out during a Read and it remains at a HIGH Z during the
entire Write cycle.
The CPHA bit must be set = 1 in the Serial Perpherial Control Register of 6805 microcomputers in order to Communicate
with these devices.
File Number 1544
_______________________________________________________________ 679


CDP68HC68R1 Datasheet
Recommendation CDP68HC68R1 Datasheet
Part CDP68HC68R1
Description CMOS 128-Word and 256-Word by 8-Bit Static RAMs
Feature CDP68HC68R1; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs) Product Preview M~~~O:I :O.
Manufacture GE
Datasheet
Download CDP68HC68R1 Datasheet




GE CDP68HC68R1
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC68R1,CDP68HC68R2
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All voltage values referenced to VB. terminal) .........................................................................-0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......••...•.•.•..••...•••.....••....•..••......................••......• -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po)'
For T.=-40 to +60° C (PACKAGE TYPE E) ............................ '" ................................................. 500 mW
ForT.=+60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T.=FULL PACKAGE-TEMPERATURE RANGE ........................................................................ 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE E ........•...................................................................................... -40° to +85°C
STORAGE TEMPERATURE RANGE (T...) .......••......•..........••.•..........•..............•..........•.......•. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59' 0.79 mm) from case for 10s max. .. ..................................................... +265°C
OPERATING CONDITIONS at TA = _40° to +85°C
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
ALL TYPES
MIN.
MAX.
DC Operating Voltage Range
3 5.5
Input Voltage Range
Serial Clock Frequency
V'H 0.7 Voo
V'L -0.3
Voo=3 V
Voo=4.5 V
ISCK
-
-
Voo +0.3
0.2 Voo
1.05
2.1
UNITS
V
MHz
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD = 3.3 V ±10%, Except as Noted
CHARACTERISTIC
Standby Device Current
loos
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Input Leakage Current, I'N
3-State Output
Leakage Current, lOUT
Operati ng Device Cu rrent
IOPER#
Input Capacitance, C'N
CONDITIONS
-
IOH=-O.4 mA, Voo=3 V
10L=0.4 mA, Voo=3 V
-
-
V'N=V'L,V'H
V'N=O V, 1-1 MHz, T.=25°C
LIMITS
CDP88HC68R1
CDP88HC88R2
MIN. TYP." MAX. MIN. TYP." MAX.
- 1 15 - 1 50
UNITS
p.A
2.7 -
--
-"
--
- 2.7
0.3 -
±1 -
±10 -
-
-
"
-
-
V
0.3
±1
p.A
±10
- 5 10 - 5 10 mA
- 4 6-
4 6 pF
-Typical values are lor T. = 25° C and nominal Voo.
#Outputs open circuited; cycle time = Min. tcyc'., duty = 100%.
"Typical input current values (high and low) lor pins 1,5,6,7, approximately 100 nA dueto presence offeedback transistor.
Pin 6 is an exception - I,n(high) typically 1 nA.
680 ______________________________________________________________



GE CDP68HC68R1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
CDP68HC68R1,CDP68HC68R2
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD = 5 V ±10%, Except al Noted
CHARACTERISTIC
Standby Device Current
loos
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Input Leakage Current, ItN
:,:I-State Output
Leakage Current, lOUT
Operating Device Current
10PE"#
Input Capacitance, C'N
CONDITIONS
-
IOH=-1.6 mA, Voo=4.5 V
10L=1.6 mA, Voo=4.5 V
IOH:::;10 /lA, Voo=4.5 V
IOL:::;10 /lA, Voo=4.5 V
-
V'N=V'L, V'H
V'N=O V, f=i MHz, TA 25°C
LIMITS
CDP68HC68R1
CDP68HC68R2
UNITS
MIN. TYP.· MAX. MIN. TYP.· MAX.
- 1 15 - 1 50 /lA
3.7 -
- 3.7 -
-
--
4.4 -
0.4 -
-
- 4.4 -
0.4
V
-
-- 0.1 - - 0.1
, ±1
, ±1
- - ±10 - - ±10 /lA
- 5 10 - 5 10 mA
46
4 6 pF
-Typical values are for TA = 25°C and nominal Voo.
#Outputs open circuited; cycle time = Min. tcyde, duty = 100%.
'Typical input current values (high and low) for pins 1,5,6,7, approximately 100 nA dueto presence of feedback transistor.
Pin 6 is an exception - !'n(high) typically 1 nA.
PIN SIGNAL DESCRIPTION
SCK (Serial Clock Input)' - This input causes serial data to
be latched from the MOSI input and shifted out on the MISO
output.
MOSI (Malter Out/Slave In)' - Data bytes are shifted in at
this pin most significant bit (MSB) first.
MISO (Master In/Slave Out)' - Data bytes are shifted out at
this pin most significant bit (MSB) first.
SS (Slave Select)' - A negative chip select input. A high
level at this input holds the serial interface logic in a reset
state.
CE (Chip Enable)" - A positive chip enable input. A low
level at this input holds the serial interface logic in a reset
state.
_
CE • SS - This is a logical function of CE and SS used
throughout this data sheet to simplify diagrams. CE' SS = 1
when pin 5 is low and pin 6 is high. CE . SS = 0 at all other
times.
'These inputs will retain their previous state if the line driving them
goes into a HIGH-Z state.
"The CE input has an internal pull-down device-if the input is
driven to a low state before going to a HIGH Z.
Shift edge, as defined by Fig. 1. There is one clock for each
data bit transferred (address as well as data bits are
transferred in groups of 8).
ADDRESS AND DATA FORMAT
The address and data bytes are shifted MSB first into the
serial data input (MOSI) and out of the serial data output
(MISO). The Address/Control byte (see Fig. 2b) contains a
Write/maa bit and a 7-bit address. Any transfer of data
requires an Address/Control byte to specify a RAM location,
followed by one or more bytes of data. Data is transferred
out of MISO for a Read and into MOSI for a Write.
Address/Control bytes are recognizable because they are
the first byte transferred following a valid CE • SS (except
for Page select bytes. see PAGE SELECTION). To transmit
a new address, CE • SS must first go false and then true
again.
_____. .1E'SS
SHIFT
{
CPOL -\
t
INTERNALl
STROBE •
SCK
FUNCTIONAL DESCRIPTION
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68R1 and CDP68HC68R2, isaserial synchronous CPOLOO{E.SS - - - - -....., SHIFT
bus for address and data transfers. The clock, which is
generated by the microcomputer, is active only during
address and data transfers. In systems using the
SCK
CDP68HC05C4, CDP68HC05C8 or CDP68HC05D2, the
inactive clock polarity is determined by the CPOL bit in the
microcomputer's control register. A unique feature of the
CDP68HC68R1 and CDP68HC68R2 is that they
MOSI--_ _ _ _ _~
automatically determine the level of the inactive clock by
OR
sampling SCK when CE. SS becomes active (see Fig. 1).
MISO
92C5-31712
Input data (MOSI) is latched internally on the Internal
Fig. 1 - Serial RAM clock (SCK) as a function of MCU clock
Strobe edge
- - - -_ _ _
and output data (MISO) is
_______________
shifted
____
out on
____
the
___
__
_
__
_
_p_ol_ar_ity_(C_P_O_L)_.
__
_
__
_
__
_
__
_
_
_
_
681







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