Read-Only Memory. CDP1833C Datasheet

CDP1833C Memory. Datasheet pdf. Equivalent


GE CDP1833C
Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1833, CDP1833C, CDP1833BC
MA7
MA6
MAO
MA4
MA3
MA2
MAl
MAO
BUS 0
BUSt
BUS2
vSS
24
23
3 22
4 21
5 2C
6 19
7 18
8 17
9 16
10 15
" 14
12 13
TOP VIEW
vOO
TPA
cn
CSI
CS2
MRD
CEO
BUS7
BUS6
eUS5
BUS4
BUS3
92CS- 2S8S9R2
TERMINAL ASSIGNMENT
CMOS 1024-Word X 8-Bit Static
Read-Only Memory
Features:
• CDP1833BC is compatible with the CDP1802BC 5 MHz microprocessor
• On-chip address latch
• Interfaces with CDP1800-series microprocessors without additional
components
• Optional programmable location within 64K memory space
• Three-state outputs
The RCA-CDP1833, CDP1833C, and CDP1833BC are static
8192-bit mask-programmable CMOS read-only memories
organized as 1024-words x 8 bits and are completely static;
no clocks are required. They will directly interface with the
CDP1800-series microprocessors without additional
comoonents.
The CDP1833, CDP1833C, and CDP1833BC respond to a
16-bit address multiplexed on 8 address lines. Address
latches are provided on-chip to store the 8 most significant
bits of the 16-bit address. By mask option, this ROM can be
programmed to operate in any 1024-word block within 64K
memory space. The polarity of the high-address strobe
(TPA), CEI, CS1, and CS2 are user mask-programmable.
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be
connected in a daisy chain to control selection of RAM
memory in a microprocessor system without additional
components.
The CDP1833C and CDP1833BC are functionally identical
to the CDP1833. The CDP1833 has a recommended
operating voltage range of4 to 10.5 volts, and the CDP1833C
and CDP1833BC have a recommended operating voltage
range of 4 to 6.5 vol~s. The CDP1833BC is designed to
interface with the CDP1802BC microprocessor.
The CDP1833, CDP1833C, and CDP1833BC are supplied
in 24-lead hermetic dual-in-line side-brazed ceramic
package (D suffix) and 24-lead dual-in-line plastic package
(E suffix). The CDP1833C IS also available In chip form (H
suffix).
"
" CD~9~3'3
~
lt2..
I
ADDR BUS
TPA
------
-----
RAM
MRD --
CEO
ADDR BUS
TPA
MRD
MWR
l~
NO-N2 MRD
TPB
r--- Q
CPU
CDPl800
SERIES
SCO SCI
INTERRUPT
DMA-IN O=T
EFI-EF4
II II
8-BIT BIDIRECTIONAL DATA BUS
Fig. 1 - Typical CDP1800 Seri6s microprocessor system.
i'r~
I/O
CONTROL
II
'2CM-2lI890RI
File Number 1135
734 __________________________________________________


CDP1833C Datasheet
Recommendation CDP1833C Datasheet
Part CDP1833C
Description CMOS 1024-Word x 8-Bit Static Read-Only Memory
Feature CDP1833C; Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ CDP1833, CDP1833C, CDP1833BC M.
Manufacture GE
Datasheet
Download CDP1833C Datasheet




GE CDP1833C
Read-Only Memories (ROMs)
CDP1833, CDP1833C, CDP1833BC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to Vss terminal)
CDP1833 ....................................................................................................... -0.5 to +11 V
CDP1833C. CDP1833BC ......................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ...................................................................... -0.5 to voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po).
ForTA = -40 to +60'C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85'C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mV/·C to 200 mW
ForTA = -55 to +100'C (PACKAGE TYPE D) ......................................................................... · 500 mW
ForTA =+100 to 125'C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mWI"C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Packages) ..................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA)'
PACKAGE TYPE D ........................................................................................... -55 to +125·C
PACKAGE TYPE E ......................................................................................... ···· .-40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ........................................................................ -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1 59 ± 0.79 mm) from case for 10 s max ................................................... +265·C
OPERATING CONDITIONS at TA = _40· to +85·C
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
LIMITS
CDP1833
CDP1833C, CDP1833BC
Min.
4
Vss
Max.
10.5
Voo
Min.
4
Vss
Max.
6.5
Voo
UNITS
V
II
A
o
I
I
8
u
2I
F
F
~
,
E
R
SIa
LI 0
~
I
E
C
CI
HI
0
0
E
R
BUS?
SUS6
BUS5
BUS4
BUS3
Voo =- 24
Vss" 12
92:CS-2:ee9IR4
Fig. 2 - Functional diagram.
_______________________________________________________________ 735



GE CDP1833C
Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1833, CDP1833C, CDP1833BC
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ± 5%, Except as noted
CONOITIONS
CHARACTERISTIC
Vo V,N
(V) (V)
Quiescent Device Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High Level
Input Low
Voltage
Input High
Voltage
Input Leakage
Current
3-State Output
Current
Operating Device
Current
Input Capacitance
-
100
-
0.4
IOL 0.5
4.6
IOH 95
-
VOL -
-
VOH -
0.5,4.5
V,L 1,9
0.5,4.5
V,H 1,9
Any
liN Input
0, 5
lOUT 0, 10
-
IDD1t -
GIN -
5
10
0, 5
0, 10
0, 5
0, 10
0, 5
0,10
0, 5
0,10
-
-
-
-
0, 5
0, 10
0, 5
0, 10
0,5
0,10
-
Output Capacitance
COUT -
-
• Typical values are for TA = 25° C and nominal Voo.
t Outputs open-circuit; cycle time = 2.5 !is
Voo
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
LIMITS
CDP1833
CDP1833C, CDP1833BC UNITS
Min. Typ." Max.
- 0.01 50
- 1 200
0.8 -
-
1.8 -
-
-0.8 -
-
-1.8 -
-a
-
0.1
- 0 0.1
4.9 5 -
9.9 10 -
- - 1.5
-- 3
3.5 -
-
7-
-
- ±10-4 ±1
- ±10-4 ±2
- ±10-4 ±1
- ±10-4 ±2
- 7 10
- 14 20
- 5 7.5
- 10 15
Min. Typ." Max.
- 0.02 200
---
0.8 -
-
--
-0.8 -
-
-
---
- 0 0.1
---
4.9 5 -
---
- - 1.5
---
3.5 -
-
---
- ±10-4 ±1
---
- ±10-4 ±1
-- -
- 7 10
---
- 5 7.5
- 10 15
!iA
mA
V
!iA
mA
pF
a-BIT BIDIRECTIONAL DATA BUS
II
~ ---
~ ----
TPA
AOOR sus
ROM
No.1
CDPIB33
\\
---
----
ROM
No.2
COPI833
AOOR BUS
~
II
RAM
-ru...~ ----
MiID
---
MiID
CEO CEI CEO cs
CHIP SELECT
SIGNAL
cs
CS
Fig. 3 - Daisy chaining CDPI833's.
"Daisy Chaining" with CEI inputs and CEO outputs is used
to avoid memory conflicts between ROM and RAM in a user
system. In the above configuration, if ROM #1 was masked-
programmed for memory locations 0000-03FF16 and ROM
#2 masked-programmed for memory locations 040016-
07FF16, for address from 0000-07FF16 the RAM would be
disabled and the ROM enabled. For locations above 07FF16
the ROM's would be disabled and the RAM enabled.
736 _____________________________________________________________







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