Static RAM. UPD2114L-1 Datasheet

UPD2114L-1 RAM. Datasheet pdf. Equivalent


NEC UPD2114L-1
NEe Microcomputers, Inc.
NEe
".PD2114L
I'PD2114L·1
I' PD2114L·2
JI. PD2114L·3
JI. PD2114L·5
DESCRIPTION
4098 BIT (1024 )( 4 BITS) STATIC RAM
The NEC I.lPD2114L is a 4096 bit static Random Access Memory organized as 1024
words by 4 bits using N-channeISilicon-gate MOS technology_ It uses fully DC stable
(static) circuitry throughout, in both the array and the decoding_ It therefore requires
no clocks or refreshing to operate and simplifies system design. The data is read out
nondestructively and has the same polarity as the input data_ Common input/output
pins are provided.
II
The I.lPD2114L is designed for memory applications where high performance, low cost,
large bit storage, and simple interfacing are important design objectives. The I.lPD2114L
is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
A separate Chip Select (CS) lead allows easy selection of an individual package when
outputs are OR-Tied.
FEATURES
Access Time: Selection from 150-450 ns
• Single +5 Volt Supply
• Directly TTL Compatible - All Inputs and Outputs
• Completely Static - No Clock or Timing Strobe. Required
• Low Operating Power - Typically 0.06 mW/8it
• Identical Cycle and Access Times
• Common Data Input and Output using Three-State Output
• High Density 18-pin Plastic and Ceramic Packages
• Replacement for 2114L and Equivalent Devices
PIN CONFIGURATION
A6
A5
A4
A3
Ao
A,
A2
IT
GND
Vee
A7
AS
Ag
1/0,
1102
1/03
1/0 4
WE
PIN NAMES
AO·Ag
Address Inputs
WE
es
110,-1/04
Write Enable
ehip Select
Data Input/Output
Vee
Power (+5V)
GND
Ground
Rev/l
59


UPD2114L-1 Datasheet
Recommendation UPD2114L-1 Datasheet
Part UPD2114L-1
Description 4K-Bit Static RAM
Feature UPD2114L-1; NEe Microcomputers, Inc. NEe ".PD2114L I'PD2114L·1 I' PD2114L·2 JI. PD2114L·3 JI. PD2114L·5 DESCRI.
Manufacture NEC
Datasheet
Download UPD2114L-1 Datasheet




NEC UPD2114L-1
JL PD2114L
A7@--
AS 16
SELECTOR
'\~EMORY ARRAY
64 ROWS
_----j@vcc
_ _ _ ~G~D
BLOCK DIAGRAM
CONTROL
Operating Temperature
Storage Temperature
Voltage on any Pin ...
. -lOOC to +80°C
-65°C to +150°C
-0.5 to 7 Volts 1
ABSOLUTE MAXIMUM
RATINGS*
Note: CD With respect to ground.
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
*Ta=25°C
Ta = aCe to 70°C; Vee"" +5V ± 10% unless otherwise noted,
PARAMETER
Input Load Current
(Alt Input Pins)
liD Leakage
Current
Power Supply
Current
f----
Power Supply
Current
Input Low Voltage
LIMITS
SYMBOL MIN TYP MAX UNIT
TEST CONDITIONS
III 10 ~A VINe 0 to 5.5V
-
ILO 10 pA eSe 2V. V I/O " O.4V to Vee
leel
leC2
V IL
-0.5
65
70
0.8
rnA VINe 5.5V. I i/O " 0 rnA.
Ta " 25°C
rnA V IN" 5.5V. 11/0 "0 rnA.
T = oOe
a
V
DC CHARACTE RISTICS
Input High Voltage
V IH 2.0
6.0 V
Output Low Current
IOL
3.2
rnA VOL" O.4V
O\.Jtput High
Current
10H
-1.0
rnA VOH = 2.4V. Vee" 4.75V
'YOH " 2.2V. Vee" 4.5V
Ta = 25°C; I = 1.0 MHz
PARAMETER
LIMITS
TEST
SYMBOL MIN TYP MAX UNIT CONDITIONS
CAPACITANCE
Input/Output Capacitance CI/O
Input Capacitance
CIN
60
8 pI
5 pI
VI/O = OV
VIN = OV



NEC UPD2114L-1
fLPD2114L
AC CHARACTE RISTICS
T,' O"C w no"c, Vee' '5V; 10%, "ol"",h"wi" oo'od,
I
PARAMETER SYMBOL
I I I I I2114L
2114L·l
liMITS
2114L·2
2114L·3
2114l·5 UNIT
TEST
I I I I I I I I IMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
CONDITIONS
READ CYCLE
1--____+-'-"'-_\-4_5_0+_+_30_0+_+_25_0+_-+2_0_0+_-+_'5_0+_-+_---j IT '" tr "If" 10 os
~-~--~~~-~~~45-0_+-~-30-0_+-~-2-50_+-_+-20-0_+-_+-'-50_+-_jCL'"lDOpF
120 100 80 70 60 load'" 1 TTL gate
Input Levels'" 0.8
F-=-=--=-=--=-=-=+---I----l--I----l--I---If--t--t--t--t--t-----Iand 2.0V
100 80 70 60 50 Vref" 1.5V
WRITE CYCLE
~w-c-"'-e-Y-"-'-T-im-,+-':.:W:::C-~4-5-0+-~3-0-0+-_+-25-0+_ _+2-,0-0_+-_+'-5-0-+--t-'-'--j 'T" Ir '" If '" 10 ns
tW~C-,"~T~,-m'--+-':.:W--~2-0-0+-~-'5-0+--+-'2-0+-_+'-2-0_+_ _+-B-O-+--t---j Cl"100 PF
WrlleRelease
Time
'WR
load" 1 TTL gate
+ ___ +--_+-_t--_+-_Outpul 3·State
tOTW
100 80
70 60
~'...:co_m...:w_c_"'~__
j - - j_ _j - f - f - - - _ t - _ I - - _ + -__
50 Input levels = 0.8
and 2.0V
Data to Wrlle
Time Overlap
'ow 200
150
'20 120
80
ns Vref '" 1.5V
Data Hold frorn
WnteTlme
'OH
Address 10 Write
Setup Time
'AW
II
TIMING WAVEFORMS
READ CYCLE CD
~---------,tRC---------"
WRITE CYCLE
~--------twc-----------~
_ _-+--,Jk.,~---tW!J)-----JI""''''7''''lr1r_ _ _ _ __
WE
DOUT
tDHtDW-<~----1
Notes:
<D We is high for Read Cycle
<V tw is measured from the latter of CS or WE going low to
the earlier of CS or WE going high.
61







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