UPD6514-2

NEe Microcomputers, Inc. NEe fL PD444/6514 fL PD444/6514·1 fL PD444/6514·2 fL PD444/6514·3 1024 x 4 BIT STATIC CMOS RAM OESCR IPTION The /JPD444/6514 is a high-speed, low power silicon gate CMOS 4096-bit static RAM organized 1024 words by 4 bits_ It uses DC stable (static) circuitry throughout and therefore requires no clock or refreshing to operate_ Data access is particularly simple since address setup times are not required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided. CSCS controls the power down feature_ In less than a cycle time after goes high - deselecting the /JPD444/6514 - the part automatically reduces its power requirements and re~ins in this low power standby mode as long as Cs is high. There is no mini- mum CS high time for device operation, although it will determine the length of time in the power down mode. When CS goes low, selecting the /JPD444/6514, the /JPD444/6514 automatically pow...