CMOS RAM. UPD447 Datasheet

UPD447 RAM. Datasheet pdf. Equivalent


NEC UPD447
NEe Microcomputers, Inc.
2048 x 8 BIT STATIC CMOS RAM
NEe
}LPD447
}LPD447-1
}L PD447-2
~rn~[~~~~illrnW
OESCR IPTI ON
The J-lPD447 is a high speed, low power, 2048 word by 8 bit static CMOS RAM
fabricated using an advanced silicon gate CMOS technology. A unique circuitry tech-
nique makes the J-lPD447 a very low operating power device which requires no clock
or refreshing to operate.
Since the device has two chip enable inputs, it is suited for battery backup applica-
tions. Minimum standby power current is drawn by this device when CE2 equals VCC
independently of the other input levels.
II
Data Retention is guaranteed at a power supply voltage as low as 2V.
TheJ-lPD447 is packaged in a standard 24-pin dual-in-line package and is plug-in
compatible with 16K EPROMs.
FEATU RES
Single +5V Supply
• Fully Static Operation - No Clock or Refreshing required
• TTL Compatible - All Inputs and Outputs
• Common Data Input and Output Using Three-State Output
• Two Chip Enable Inputs for Battery Operation
• Max Access/Min Cycle Times Down to 120 ns
~ Low Power Dissipation; 45 mA Max Active/100 J-lA Max Standby/
10 J-lA Max Data Retention
• Data Retention Voltage - 2V Min
• Standard 24-Pin Plastic imd Ceramic Packages
• Plug-in Compatible with 16K EPROMs
PIN CONFIGURATION
2
3
4
5
6
Al
8
1/01 9
10
J-lPD
447
12
24 VCC
23 Aa
22 Ag
21 WE
20 CEI
19 Al0
18 CE2
17 I/oa
16 1/07
1/06
14 1/05
13 1/04
PIN NAMES
AO-AlO
WE"
Address Inputs
Write Enable
CE1-m Ch ip Enable Inputs
1/0\-1/08 Data Input/Output
VCC
Power (+5V)
GND
Ground
TRUTH TABLE
CEI CE2 WE
MODE
I/O ICC
X H X NOT SELECTED HZ STANDBY
H X X NOT SELECTED HZ ACTIVE
L L L WRITE
DIN ACTIVE
L L H READ
DOUT ACTIVE
105


UPD447 Datasheet
Recommendation UPD447 Datasheet
Part UPD447
Description 2K x 8 BIT STATIC CMOS RAM
Feature UPD447; NEe Microcomputers, Inc. 2048 x 8 BIT STATIC CMOS RAM NEe }LPD447 }LPD447-1 }L PD447-2 ~rn~[~~~~ill.
Manufacture NEC
Datasheet
Download UPD447 Datasheet




NEC UPD447
j'PD447
A4
AS
AS DDRESS
A7 8UFFER
As
A9
A10---t......_ .....
ROW
DECODER
I/~' _ _-+_ _....
I
I
1100 ---+-....-+1
CELL ARRAY
128 ROWS
128 COLUMNS
SENSE SWITCH
COLUMN
DECODER
OU11'UT
DATA
CONTROL
BLOCK DIAGRAM
CE2
CE1-(::I:lH!i-I
WE~~~-'----------------------~
Supply Voltage ............. .
Input or Output Voltage Supplied
Storage Temperature Range .. .
Operating Temperature Range .. .
.......... 7.0V
-0.3 to VCC + 0.3V
-55°C to 125°C
. .... O°C to 70°C
ABSOLUTE MAXIMUM
RATINGS*
COMMENT Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
*Ta = 2SOC
Vee = 5V :!: 10%, Ta = O°C to 70°C
LIMITS
PARAMETER
TEST
SYMBOL CONDITIONS
~D447·2
MIN TVP MAX-
~PD447·1
MIN TYP MAX
""'D447
MIN TYP MAX
UNIT
Input High Voltage
V,H
2.2 Vee +0.3 2.2 Vee + 0.3 2.2 VCC+ O•3
Input Low Voltage
V,L
....3 0.8 ....3 0.8 -0.3 0.8 V
Input leakage Current ILl VIN"'O-VCC -1.0
1.0 -1.0
1.0 -1.0
1.0· .A
I/O Leakage Current
VCE2 = V1H
ILO
-1 ..0
VI/O "O-Vee
1.0 -1.0
1.0 -1.0
1.0 .A
Operating Supply Current
IceA'
ICCA2
VCE2" vlL
11/0- 0
MIN TCVCLE
VCE2" Vil.
11/0"'0
DC CURRENT
30 .s
10
2S 3.
10
20 30
10
mA
mA
Standby Current
Output High Voltage
Output low Voltage
ICCS
VCE2 = Vee
VIN = 0- Vec
VOH IOH =-1.0mA
VOL. IOl = 2.0mA
2.'
100
0.'
2.4
100
0.'
2.'
100 .A
0.' V
DC CHARACTERISTICS
Ta = 25°C, f = 1.0 MHz
PARAMETER
SYMBOL
Input Capacitance
CIN
Input/Output Capacitance CI/O
LIMITS
MIN MAX UNIT
TEST
CONDITIONS
6 pF. VIN = OV
8 pF VI/O = OV
CAPACITANCE
106



NEC UPD447
JL PD447
AC CHARACTERISTICS
-
PARAMETER
Read Cvcle Time
Access Time
Chip Enable (CEl) to Output Valid
Chip Enable (CE2) to Output Valid
Output Hold from Address Change
Chip Enable (CE 1) to Output in LZ
Chip Enable (CE2) to Output in LZ
Chip Enable (CEl) to Output in HZ
Chip Enable (CE2) to Output in HZ
READ CYCLE
SYMBOL
'RC
'A
'C01
'CO2
'OH
'LZl
'LZ2
'HZl
'HZ2
"PD447-2
MIN MAX
120
120
60
120
20
10
10
60
60
LIMITS
"PD447-1
MIN MAX
150
150
75
150
20
10
10
75
75
"PD447
MIN MAX
200
200
100
200
20
10
10
100
100
UNIT
n,
n'
n,
n,
n,
n,
n,
n,
n,
II
-
PARAMETER
Write Cycle Time
Chip Enable (CE1) to End of Write
Chip Enable (CE2) to End of Write
Address Setup Time
Write Pulsewidth
Write Recovery Time
Write Enable to Output in HZ
Output Active from End of Write
Data Valid to End of Write
Data Hold Time
WRITE CYCLE
SYMBOL
'WC
tCWl
tCW2
tAW
'WP
'WR
twz
tow
tow
tOH
"PD447-2
MIN MAX
120
100
100
0
LIMITS
"PD447-1
MIN MAX
150
125
125
0
"PD447
MIN MAX
200
170
170
0
UNIT
n,
n,
n,
n,
100 125 170
000
60 75 100
20 20 20
60 75 100
n'
n,
n,
n,
n,
0 a 0 n'
LOWVCC
DATA RETENTION
Ta = O°C to 70"C
PARAMETER
SYMBOL
TEST
LIMITS
CONDITIONS MIN TYP MAX UNIT
V CC for Data Retention
VCCDR VIN=O-VCC, 2.0
VCE2 = VCC
V
Data Retention Current
ICCDR
VCC = 3.0V,
VIN=O-VCC
Vffi=Vcc
0.1 10 IJ,A
Chip Disable to Data Retention Time tCDR
0 ns
Operation Recovery Time
tR
tRC ns
107







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