ONLY MEMORY. UPB406-2 Datasheet

UPB406-2 MEMORY. Datasheet pdf. Equivalent


NEC UPB406-2
NEe Microcomputers, Inc.
4098-BIT BIPOLAR TTL
PROGRAMMABLE
READ ONLY MEMORY
NEe
JLPB406 JLPB426
JLPB406-1 JLPB426-1
JL PB406-2 JL PB426-2
DESCRIPTION
The IlPB406 and IlPB426 are high-speed, electrically programmable, fully-decoded
4096-bit TTL read-only memories. On-chip address decoding, two chip·enable inputs
and open-collector/three-state outputs allow easy expansion of memory capacity. The
IlPB406 and IlPB426 are fabricated with logic level zero (low); logic level one (high)
can be electrically programmed into the selected bit locations. The same address
inputs are used for both programming and reading.
FEATURES
1024 WORD X 4 BIT Organization (Fully Decoded)
• TTL Interface
• Fast Read Access Time: 50 ns max. (IlPB406-2, IlPB426·2)
• Medium Power Consumption: 500 mW TYP.
• Two Chip Select Inputs for Memory Expansion
• Open-Collector Output (IlPB406)/Three-State Outputs
(Il PB426)
• Ceramic and Plastic lS-Lead Dual In-Line Packages
• Fast Programming Time: 200 Ils/bit TYP.
• Compatibility with: HPROM HM-7642/7643 type and Equivalent Devices
(as a ROM)
• A.i.M. (Avalanche Induced Migration) Technology
PIN CONFIGURATION A6
A5
A4
A3
AO
Al
A2
CSl
GND
VCC
A7
AS
Ag
01
02
03
04
CS2
PIN I\lAMES
AO-Ag
Address Inputs
01-0 4
Data Outputs
CS1, CS2
Chip Selects
VCC
Power (+5V)
GND
Ground
Rev/l
133


UPB406-2 Datasheet
Recommendation UPB406-2 Datasheet
Part UPB406-2
Description 4K-BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY
Feature UPB406-2; NEe Microcomputers, Inc. 4098-BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY NEe JLPB406 JLPB426 JLP.
Manufacture NEC
Datasheet
Download UPB406-2 Datasheet




NEC UPB406-2
Jo'PB406/426
Programming
A logic one can be permanently programmed into a selected bit location by using
special equipment (programmer). First, the desired word is selected by the ten address
inputs in TTL levels. Either or both of the two chip select inputs must be ata logic
one (high); Secondly, a train of high current programming pulses is applied to the
desired output. After the sensed voltage indicates that the selected bit is in the logic
one state, an additional pulse train is applied, then is stopped.
Reading
To read the memory, both of the two chip select inputs should be held at logiC zero
(low). The outputs then correspond to the data programmed in the selected words.
When either or both of the two chip select inputs are at logic one (high). all the
....-----,outputs will be high (floating) .
OPERATION
BLOCK DIAGRAM
RI-_.... OUTPUT 1 - - - - - 0
BUFFER
01
4096 BIT
(64 X 64)
MEMORY CELLS
ARRAY
1-+----003
WORD DECODER
Operating Temperature .......•.•.....•.•.••........• -2SoC to +7Soe
Storage Temperature. . . . . . . • . . . . . . . . . . . . . . . . . • . . . .. -6Soe to +lS0oe
All Output Voltages ...•••.•.............•.... ,... -O.S to +S.S Volts
All Input Voltages . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . -O.S to +S.S Volts
Supply Voltage Vee. . . . . . . • . . . . • . . . . • . . . . . . . . . . .. -o.S to +7.0 Volts
Output Currents. . . . • . • . . . . • . . . . . . . . . . . . . . . . . . • . • . . . . . . .. SO mA
ABSOLUTE MAXIMUM
RATINGS*
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanellt
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions abOve those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
134



NEC UPB406-2
p.PB406/426
PROGRAMMING
SPECI FICATION
It is imperative that this specification be rigorously observed in order to correctly pro·
gram the ).IPB406 and ).IPB426. NEe will not accept responsibility for·any device
found to be defective if it were not programmed according to this specification.
A typical programming operation is performed by first sensing, then programming,
then sensing again to see if the word to be programmed has reached the desired
state. Either or both of the two chip enable inputs must be at a logic one (high).
Sensing is accomplished by forcing a 20 mA current into the selected location via the
output. The sense measurement is to ensure that the voltage required to force this
20 mA current is less than the reference voltage. If this condition is satisfied, then
that bit location is in the logic "1" (high) state.
Programming is accomplished by forcing a 200 mA current into the selected bit via the
output. This current pulse is applied for 7.5).1s and then the location is sensed before
a second programming current pulse is applied. This process is continued until that
location is altered to the "1" state. A bit is judged to be programmed when two
successive sense readings 10).ls apart with no intervening programming pulse pass the
limit. When this condition has been met, four additional pulses are applied, then the
sense current is terminated.
CHARACTER ISTIC
Ambient Temperature
Programming Pulse
Amplitude
Clamp Voltage
Ramp Rate (both in Rise
and in Fall)
Pulse Width
Duty Cycle
Sense Current
Amplitude
Clamp Voltage
Ramp Rate
Sense Current Interruption
before and after address
change
Programming VCC
Maximum Sensed Voltage
for programmed "1"
Delay from trailing edge of
programming pulse before
sensing output voltage
LIMIT
25 ± 5
200 ± 5%
28 + 0% - 2%
70 MAX.
7.5 ± 5%
70% MIN.
20 ± 0.5
28+0%-2%
70 MAX.
UNIT
·C
mA
V
VI"..
"..
mA
V
VI"..
10MIN.
5.0+ 5%-0%
7.0 ± 0.1
"s
V
V
0.7MIN.
"s
NOTES
15V pointl
1500 load.
15V pointl
1500 load.
~I~- - ---I
0.7"sMIN.
Additional Puise Train
• _ 28V Clamp
=~~~~~::::~~::ampUI.e
7.5 ":
·10".
~"'10"S
----·-20 mA Sensing (Before PI
-~-->--,":~72.00VmARSeefn.Sing (AfterP)
~
'GND
Output Voltage Sensing
Figure 2 - Typical Output Voltage Waveform
135





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