CHIP MICROCOMPUTER. UPD7520 Datasheet

UPD7520 MICROCOMPUTER. Datasheet pdf. Equivalent


NEC UPD7520
NEe Microcomputers, Inc.
NEe
,.,.PD7520
4-BIT SINGLE CHIP MICROCOMPUTER
DESCR IPTION
The j.lPD7520 is a IlCOM-75 4-bit single chip microcomputer with a Programmable
Display Controller capable of directly driving a multiplexed 8-segment, 8-digit LED
Display. It has a 768 x 8 ROM, a 48 x 4 RAM, and 24 I/O lines for communication
with and control of external circuitry. The j.lPD7520 is manufactured with a low-
power consumption PMOS process, allowing use of a single power supply between
-6V and -10V. The j.lPD7520 executes 47 instructions of the j.lCOM-75 instruction
set, and is available in a low-cost 28-pin plastic dual-in-line package.
FEATU RES
768 x 8 Bit ROM
• 48 x 4 Bit RAM
• 20 j.lS Instruction Cycle Time, Typical
• 47 Powerful Instructions
- Table Look-Up Capability with LAMT Instruction
• 2-Level Subroutine Stack
• One 4-Bit Input Port
• One 4-Bit I/O Port
• One 2-Bit Output Port (Capable of Driving Piezo Element)
• Programmable Display Controller
- 6 LED Direct Digit Drive Outputs (8 Possible Using P40-1)
8 LED Direct Segment Drive Outputs
Selection of a 4, 5, 6, or 8-Digit Display Strobe Cycle
Can Directly Drive 8-Segment, Multiplexed Displays,
or up to an 8 x 8 Dot Matrix
Automatic Synchronization of Segment and Digit Signals,
Transparent to Program Execution
- Segment Outputs also Function as Latched, 8-Bit Parallel Output Port
• Built-In Clock Signal Generation Circuitry
• Built-In Reset Circuitry
• Single Power Supply, Variable from -6V to -10V
• Low Power Consumption: 45 mW, Typical
• P-Channel MOS Technology
• 28-Pin Plastic Dip
PIN CONFIGURATION
P31
P30
P13
P12
P11
P10
P43
P42
P41
P40
T5
T4
T3
VSS
ClK
RESET
VGG
So
S4
S1
S5
S2
S6
S3
S7
TO
T1
T2
PIN NAMES
So -S7
TO-T5
P10 - P13
P30 - P3 1
P40 - P43
ClK
RESET
VGG
VSS
Segment Drive
Output Port S
Digit Drive
Output Port T
Input Port 1
Output Port 3
Input/Output Port 4
Clock Input
Reset
Power Supply
Negative
Ground
II
227


UPD7520 Datasheet
Recommendation UPD7520 Datasheet
Part UPD7520
Description 4-BIT SINGLE CHIP MICROCOMPUTER
Feature UPD7520; NEe Microcomputers, Inc. NEe ,.,.PD7520 4-BIT SINGLE CHIP MICROCOMPUTER DESCR IPTION The j.lPD75.
Manufacture NEC
Datasheet
Download UPD7520 Datasheet




NEC UPD7520
OCCHARACTERISTICS
Ta = -10·C to +70·C, VGG· -6V 10 -10V
~PD7520
PARAMETER SYMBOL
Input Voltage
High
Input Voltage
Low
Clock Voltage
High
Clock Voltage
Low
Input Current
High
Input Leakage
Current High
Input Leakage
Current Low
Clock Current
High
Clock Current
Low
Output Voltage
Low
Output Current
High
VIH
VIL
V</>H
V</>L
IIH
ILiH
ILILl
ILlL2
I</>H
I</>L
VOL
IOHl
IOH2
IOH3
IOH4
Output Current
l.9w
lOLl
IOL2
LIMITS
MIN TYP MAX
-2
-1.8
VGGH.S
VGG+O.8
UNIT
V
V
TEST CONDITIONS
Ports 1,4, RESET VGG =-9V ± lV
VGG --6V to-l0V
Ports 1,4, RESET VGG=-9V±lV
VGG =-6V to-l0V
-OB V
CLK, External Clock
-S.o
4S
40
V CLK, External Clock
I200
200
jJA
Port 1, RESET LVI =ov, VGG =-9V ± lV
VI - OV, VGG - -6V to -10V
+S jJA Port 4, VI = OV
-S jJA Port 1, RESET, VI =-10V, VGG =-10V
-S jJA Port 4, VI =-10V
0.5 mA ClK, External Clock, V.pH = OV,
VGG =-9V ± lV
ClK, External Clock, V.pL =-SV,
-2.1 mA
VGG --9V ± lV
VGG+O.5
V Port 3, No load
-1.0
-0.6
-2.0
-1.2
-S
-3
-1
-24
-13
-9
1
0.1
0.3
0.1
4.5
-10
-6
-3
-48
-27
-18
2
02
0.6
02
9
12
Vo =-LOV, VGG =-9V ± lV
mA Port 3,' Vo --1.0V, VGG --6V
VO=-1.0V,VGG=-9V± lV
mA
Port 4,
Vo --LOV. VGG --6V
Vo =-2.0V, VGG =-9V ± lV
mA Port S, Vo --2.0V, VGG =-6V
Vo =-1.0V, VGG· -6V to -10V
Vo =-2.0V, VGG =-9V ± lV
<DmA Port i" Vo =-1.0V, VGG =-9V ± lV
VO--l.0V,VGG 6V
Vo = VGG + 1.SV, VGG =-9V ± lV Q)
Vo VGG +3.SV, VGG =-9V ± lV
CDmA Port 3, VO= ':'4.5V, VGG =-6V
Vo - -2.5V, VGG - -6V
VO· VGG +5.0V, VGG =-9V ± lV
mA PortS,
Vo = VGG + 3.5V, VGG =-6V to -10V'
Output Leakage
Current High
ILOH
+5 jJA Ports 4, TL.YO =OV
Output Leekage
Current' Low
Supply Current
ILOL
IGG·
-5 jJA Ports 4, T, Vo =-10V
-S ~.8 mA Te = 25·C. VGG = -9V, No Load
G>Note: Current within 2.5 ms after turning to the low level, (Ta = 25·C).
228



NEC UPD7520
,u.PD7520
BLOCK DIAGRAM
VGG_
Vss_
SO_7
TO-S
Internal Registers
The ALU, the Accumulator, and the Carry Flag together comprise the central por-
tion of the IlPD7520 architecture_ The ALU performs the arithmetic and logical
operations, and checks for various results_ The Accumulator stores the results gener-
ated by the ALU, and acts as the major interface point between the RAM, the I/O
ports, and the Hand L registers_ The Carry Flag can be addressed directly, and can
be set during an addition_
FUNCTIONAL
DESCRIPTION
Data Pointer Registers
The 2-bit H register and 4-bit L register are two registers which reside externally to
the 48 x 4 bit RAM _They function as the Data Pointer, addressing the rows and
columns of the RAM, respectively _They are individually accessible, and the L regis-
ter can be automatically incremented or decremented_
RAM
The IlPD7520 has a static 48 x 4 bit RAM organized into 3 rows by 16 columns_ The
RAM is used for general purpose data storage or data transfers, and is also used to
store Display Data for access by the segment latch of the Display Controller.
ROM
The ROM is the mask-programmable portion of the f-lPD7520 which stores the appli-
cation program. It is organized into a single 768 x 8 bit field. Execution of the pro-
gram resident in the ROM is independent of field or page boundary limitations.
Program Counter and Stack Register
The Program Counter is a 1O-bit register which contains the address of a particular
instruction being executed. It is incremented during normal operation, but can be
modified by various JUMP and CALL instructions. The Stack Register is a LI FO
push-down stack register used to save the value of the Program Counter when a sub-
routine is called. It is' organized as 2 words x 10 bits to accommodate 2 levels of
subroutine calls.





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