Document
NEe Microcomputers, Inc.
ttt{EC
P.PD8041
UNIVERSAL PROGRAMMABLE PERIPHERAL INTERFACE - 8·BIT MICROCOMPUTER
DESCR IPT ION
The tLPDB041 is a programmable peripheral interface intended for use in a wide range of microprocessor systems. Functioning as a totally self·sufficient controller, the
tLPDB041 contains an B-bit CPU, 1K x B program memory, 64 x B data memory, I/O
lines, counter/timer, and clock generator in a 40-pin DIP. The bus structure, data regis-
ter, and status register enable easy interface to B04B, BOBOA, or BOB5A based systems.
FEAT U R ES
• Fully Compatible with B04B, BOBOA and B085A Bus Structure • B-Bit CPU with 1K x B ROM, 64 x B RAM, B-Bit Timer/Counter, 18 I/O Lines
• 4-Bit Status and 8-Bit Data Register for Asynchronous Siave-to-Master Interface • Interrupt, DMA, or Polled Operation • Expandable I/O • Two Interrupts • 40-Pin Plastic or Ceramic DIP • Single +5V Supply
PIN CONFIGURATION
TO
X1 x2 RESET
55
cs
EA
RD AO
WR
SYNC
DO D1 D2
D3 D4 D5
D.