N-CHANNEL MICROPROCESSOR. UPD780 Datasheet
NEe Microcomputers, Inc.
8·BIT N·CHANNEL MICROPROCESSOR
COMPLETELY Z80™ COMPATIBLE
DESC RIPTI ON
The pPD780 and pPD780-1 processors are single-chip microprocessors developed from
third-generation technology,Their increased computational power produces higher
system through-put and more efficient memory utilization, surpassing that of any
second-generation microprocessor, The single voltage requirement of the t1PD780 and
IlPD780-1 processors makes it easy to implement them into a system. All output sig-
nals are fully decoded and timed to either standard memory or peripheral circuits. An
N-channel, ion-implanted, silicon gate MOS process is utilized in implementing the
The block diagram shows the functions of the processor and details the internal register
structure. The structure contains 26 bytes of Read/Write (R/W) memory available to
the programmer. Included in the registers are two sets of six general purpose registers,
which may be used individually as S-bit registers, or as 6-bit register pairs. Also
included are two sets of accumulator and flag registers.
Through a group of exchange instructions the programmer has access to either set of
main or alternate registers. The alternate register permits foreground/background mode
of operation, or may be u~ed fv( fast interrupt response. A l6-bit stack pointer is also
included in each processor, simplifying implementation of multiple level interrupts,
permitting unlimited subroutine nesting, and simplifying many types of data handling.
The two 16-bit index registers simplify implementation of relocatable code and manipu-
lation of tabular data. The refresh register automatically refreshes external dynamic
memories. A powerful interrupt response mode uses the I register to form the
upper 8 bits of a pointer to an interrupt service address table, while the interrupting
apparatus supplies the lower 8 bits of the pointer. An indirect call will then be made to
service this address.
• Single Chip, N-Channel Silicon Gate Processor
• 158 Instructions - Including all 78 of the 8080A Instructions, Permitting Total
• New 4-,8-, and 16-8it Operations Featuring Useful Addressing Modes such as
Indexed, Bit and Relative
• 17 Interndl Registers
• Three Modes of Rapid Interrupt Response, and One Non-Maskable Interrupt
• Directly Connects Standard Speed Dynamic or Static Memories, with Minimum
• Single-Phase +5 Volt Clock and 5 VDC Supply
• TTL Compatibility
• Automatic Dynamic RAM Refresh Circuitry
• Available in Plastic Package
TM:Z80 is a registered trademark of Zilog, Inc_
MAIN REGISTER SET
AL TERNATE REGISTER seT
INTERRUPT VECTOA I
MEMORY REFRESH R
SPECIAL PURPOSE REGISTERS
3-State Output, active high. Pins AO-A15 constitute a
16-bit address bus, which provides the address for
memory and I/O device data exchanges. Memory
capacity 65,536 bytes. AO-A7 is also needed as
3-State input/output, active high. Pins 00-07 compose
an 8-bit, bidirectional data bus, used for data exchanges
with memory and I/O devices.
Output, active low. Ml indicates that the machine cycle
in operation is the op code fetch cycle of an instruction
3-State output, active low. MREO indicates that a valid
address for a memory read or write operation is held in
3-State output, active low. The I/O request
signal indicates that the lower half of the address bus
holds a valid address for an I/O read or write operation.
The iORQ signal is also used to acknowledge an
interrupt command, indicating that an interrupt
response vector can be placed on the data bus.
3-State output, active low. R0 indicates that the
processor is requesting data from memory or an
I/O device. The memory or I/O device being addressed
should use this signal to gate data onto the data bus.
3·State output, active low. The memory write signal
indicates that the processor data bus is holding valid
data to be stored in the addressed, memory or I/O
Output, active low. RFSH indicates that a refresh
address for dynamic memories is being held in the
lower 7·bits of the address bus. The MREO signal
should be used to implement a refresh read to all
Output, active low. HALT indicates that the processor
has executed a HALT software instruction, and will
not resume operation until either a non·maskable or a
maskable (with mask enabled) interrupt has been
implemented. The processor will execute NOP's while
halted, to maintain memory refreSh activity.
Input, active low. WAIT indicates to the processor
that the memory or I/O devices being addressed are
not ready for a data transfer. As long as this signal is
active, the processor will reenter wait states.
Input, active low. The INT signal is produce;!l by I/O
devices. The request will be honored upon completion
of the current instruction, if the interrupt enable
flip-flop (I F F) is enabled by the internal software.
There are three modes of interrupt response..
Mode o'ls identical to 8080 interrupt response mode.
The Mode 1 response is a restart location at 0038H.
Mode 2 is for simple vectoring to.an interrupt service
routine anywhere in memory.
Input, active low. The non-maskable interrupt has a
higher priority than INT. It is always acknowledged at
the end of the current instruction, regardless oft~
status of the interrupt enable fUp-flop. When the NMI
signal is given, the I'PD780 processor automatically
restarts to lo~ation OOS6H.
26 RESET Reset
25 BUSRO Bus Request
Input, active low. The RESET signal causes the
processor to reset the interrupt enable flip·flop (IFF),
clear PC and I and R registers, and set interrupt to
8080A mode. During the reset time, the address bus
and data bus go to a state of high impedance, and all
control output signals become inactive, after which
processing continues at OOOOH.
Input, active low. IiIUSRO has a higher priority than
NMI, and is always honored at the end of the current
machine cycle. It is used to allo,w other devices to
take control over the processor address bus, data bus
signals; by requesting that they go to a state of high
23 BUSAK Bus Acknowledge Output, active low. tiUSAK is used to inform the
requesting device that the processor address bus,
data bus and 3·state control bus signals have entered
a state of high impe<lance, and the exiern~1 device can
now take control of these signals.