N-CHANNEL MICROPROCESSOR. UPD8080AF Datasheet
NEe Microcomputers, Inc.
JLPD8080AF 8-BIT N-CHANNEL
The IlPD8080AF is a complete 8-bit parallel processor for use ill general purpose
digital computer systems_ It is fabricated on a single LSI chip using N-channel silicon
gate MOS process, which offers much higher performance than conventional micro-
processors (1.28Ils minimum instruction cycle). A complete microcomputer system
is formed when the IlPD8080AF is interfaced with I/O ports (up to 256 input and 256
output ports) and any type or speed of semiconductor memory. It is available in a
40 pin ceramic or plastic package.
• 78 Powerful Instructions
• Three Devices - Three Clock Frequencies
pPD8080AF - 2.0 MHz
IlPD8080AF-2 - 2.5 MHz
uPD8080AF-l - 3.0 MHz
• Direct Access to 64K Bytes of Memory with 16-Bit Program Counter
• 256 8-Bit I nput Ports and 256 8-Bit Output Ports
• Double Length Operations Including Addition
• Automatic Stack Memory Operation with 16-Bit Stack Pointer
• TTL Compatible (Except Clocks)
• Multi-byte Interrupt Capability
• Fully Compatible with Industry Standard 8080A
• Available in either Plastic or Ceramic Package
The IlPD8080AF contains six 8-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit. The IlPD8080AF also provides
decimal arithmetic capability and it includes 16-bit arithmetic and immediate operators
which greatly simplify memory address calculations, and high speed arithmetic
The IlPD8080AF utilizes a 16-bit address bus to directly address 64K bytes of
memory, is TTL compatible (1.9 mAl, and utilizes the following addressing
modes: Direct; Register; Register Indirect; and Immediate.
The IlPD8080AF has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (LI FO) stack to store/retrieve the contents of the
accumulator, the flags, or any of the data registers.
The IlPD8080AF also contains a 16-bit stack pointer to control the addressing of this
external stack. One of the major advantages of the stack is that multiple level inter-
rupts can easily be handled since complete system status can be saved when an inter-
rupt occurs and then restored after the interrupt is complete. Another major advantage
is that almost unlimited subroutine nesting is possible.
This processor is designed to greatly simplify system design. Separate 16-line address
and 8-line bidirectional data buses are employed to allow direct interface to memories
and I/O ports. Control signals, requiring no decoding, are provided directly by the
processor. All buses, including the control bus, are TTL compatible.
Communication on both the address lines and the data lines can be interlocked by
using the HOLD input. When the Hold Acknowledge (HLDA) Signal is issued by the
processor, its operation is suspended and the address and data lines are forced to be in
the FLOATING state. This permits other devices, such as direct memory access chan-
nels (DMA), to be connected to the address and data buses.
The IlPD8080AF has the capability to accept a multiple byte instruction upon an inter·
rupt. This means that a CALL instruction can be inserted so that any address in the
memory can be the starting location for an interrupt program. This allows the assign-
ment of a separate location for each interrupt operation, and as a result no polling is
required to determine which operation is to be performed.
NEC offers three versions of the IlPD8080AF. These processors have all the features
of the IlPD8080AF except the clock frequency ranges from 2.0 MHz to 3.0 MHz.
These units meet the performance requirements of a variety of systems while maintain-
ing software and hardware compatibility with other 8080A devices.
A8 0-15 (THREE STATE)
TIMING a CONTROL
AB _ BUFFER
BIT 7- S:SIGN
DBO_7 (THREE STATEI
81T 6 - Z:ZERO
alT 4 - ACY:AU)CILIARY CARRY
81T 3- O·AL.WIIYS·O·
81T I -I AlWAYS "I-
A15 - AO
The address bus is used to address memory (up to 64K S·bit words)
or specify the I/O device number (up to 256 input and 256 output
devices), AO is the least significant bit.
3·10 D7 - DO
Data Bus (input/
The bidirectional data bus communicates between the processor,
memory, and 1/0 devices for instructions and data transfers. Dur-
ing each sync time, the data bus contains a status word that
describes the current machine cycle. DO is the least significant bit.
Vas Supply Voltage '-5V ± 5%
If the RESET signal is activated, the program counter is cleared.
aAfter RESET, the program starts at location in memolY. The
INTE and HLDA flip·flops are also reset. The flags, accumulator,
stack pointer, and registers are not cleared. (Note: External syn·
chronization is not required for the RESET input signal which
must be active for a minimum of 3 clock periods.)
HOLD requests the processor to enter the HOLD state. The HOLD
state allows an external device to gain control of the /lPD8080AF
address and data buses as soon as the ,uPD8080AF has completed
its use of these buses for the current machine cycle. It is recog·
··nized under the following conditions:
The processor is in the HALT state.
The processor is in the T2 or TW stage and the READY signal
As a result of entering the HOLD state, the ADDR ESS BUS
(A15 - AO) and DATA BUS (07 - 00) are in their high imped·
ance state. The processor indicates its state on the HOLD
ACKNOWLEDGE (HLDAI p;n.
The ,uPDB080AF recognizes an interrupt request on this line at
the end of the current instruction or while halted. If the
pPD80BOAF is in the HOLD state, or if the Interrupt Enable
Hip-flop is reset, it will not honor the request.
Phase Two (input)
Phase two of processor clock.
INTE indicates the content of the internal interrupt enable flip-
flop. This flip·flop is set by the Enable (EI) or reset by the
Disable (01) interrupt instructions and inhibits interrupts from
being accepted by the processor when it is reset. INTE is auto-
matically reset Jdisabling further interrupts) during T 1 of the
instruction fetch cycle (M 1) when an interrupt is accepted and
is also reset by the RESET signal.
Data Bus In
DBIN indicates that the data bus is in the input mode. This
signal is used to enable the gating of data onto the ,uPD8080AF
data bus from memory or input ports.
WR is used for memory WR ITE or I/O output control. The data
on the data bus is valid while the WR signal is active (WR ::= 0).
The SYNC signal indicates the beginning of each machine cycle.
+5V ± 5%
Phase One (input)
HLOA is in response to the HOLD signal and indicates that the
data and address bus will go to the high impedance state. The
··HLDA signal begins at:
T3 for READ memory or input operations.
The clock period following T3 for WRITE memory or
In either case, the H LOA appears after the rising edge of ¢1 and
high impedance occurs after the rising edge of ¢2.
Phase one of processor clock.
23 READY Ready (input)
The READY signal indicates to the /-IP08080AF that valid mem-
ory or input data is available on the ,uPDB080AF data bus.
READY ;s used to synchronize the processor with slower memory
or t/O devices. If after sending an address out, the ,uPD80BOAF
does not receive a high on the READY pin, the ,uPDB080AF enters
a WAIT state for as long as the READY pin is low. (READY can
also be used to single step the processor.)
The WAIT signal indicates that the processor is in a WAIT state.
VDO Supply Voltage +12V ± 5%
CDNote_ After the EI inuruction, the ,..PD8080AF accepts interrupts on the second instruction follOllvtng the EI. ThiS
allo'NS proper execution of the RET instruction if an interrupt operation is pending after the service routine.