8051-Based MCU. MG86FE104 Datasheet

MG86FE104 MCU. Datasheet pdf. Equivalent

Megawin MG86FE104
8051-Based MCU
Data Sheet
Version: A1.5
is document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2005 All rights reserved.
2015/05 version A1.5

MG86FE104 Datasheet
Recommendation MG86FE104 Datasheet
Part MG86FE104
Description 8051-Based MCU
Feature MG86FE104; 8051-Based MCU MG86FE/L104 Data Sheet Version: A1.5 is document contains information on a new prod.
Manufacture Megawin
Download MG86FE104 Datasheet

Megawin MG86FE104
MG86FE/L104 Data Sheet

Megawin MG86FE104
1-T 80C51 Central Processing Unit
MG86FE/L104 with 4K Bytes flash ROM
ISP memory zone could be optioned as 0.5KB/1KB/1.5KB……3.5KB
Flexible IAP size.
Code protection for flash memory access
Flash write/erase cycle
For 0.5K IAP, the MTP of IAP write cycle is 2,000 times.
For 1.0K IAP, the MTP of IAP write cycle is 1,000 times
Flash data retention: 100 years at 25
MG86FE/L104 Flash space mapping (Default)
AP Flash0000h~07FFh
IAP Flash0800h~0BFFh
ISP Flash0C00h~0FFFh)(ISP Boot code
On-chip 256 bytes scratch-pad RAM
Interrupt controller
6 sources, four-level-priority interrupt capability
Two external interrupt inputs, nINT0 and nINT1.
All external interrupts support High/Low level or Rising/Falling edge trigger.
Two 16-bit timer/counters, Timer 0 and Timer 1.
T0CKO on P34 and T1CKO on P35.
X12 mode enabled for T0/T1.
Enhanced UART (S0)
Framing Error Detection
Automatic Address Recognition
a speed improvement mechanism (X2/X4 mode)
4 channel UART repeater mechanism
Keypad Interrupt on all GPIO.
Programmable Watchdog Timer
One time enabled by CPU or power-on
Sourced from on-chip low frequency oscillator (ILRCO)
Interrupt CPU or Reset CPU on WDT overflow
Support WDT function in power down mode
Maximum 18 GPIOs in 20-pin package.
P3 can be configured to quasi-bidirectional, push-pull output, open-drain output and input only.
P1, P4.0 and P4.1 can be configured to push-pull output or open-drain output.
P4.0, P4.1 and P3.6 are shared with XTAL2, XTAL1 and RST.
All GPIOs have wakeup capability.
Multiple power control modes: idle mode, power-down mode, slow mode, sub-clock mode, watch mode and
monitor mode.
All interrupts can wake up IDLE mode
6 sources to wake up Power-Down mode
Slow mode and sub-clock mode support low speed MCU operation
Watch mode supports WDT to resume CPU in power down
Monitor mode supports BOD0 to resume CPU in power down (L-series only)
Brown-Out Detector: VDD 4.2V for E-series and VDD 2.4V for L-series
Interrupt CPU or reset CPU
Wake up CPU in Power-Down mode (L-series only)
MG86FE/L104 Data Sheet

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