8051-Based MCU. MG82FL564 Datasheet

MG82FL564 MCU. Datasheet pdf. Equivalent

Megawin MG82FL564
8051-Based MCU
Data Sheet
Version: A1.01
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2012 All rights reserved.
2015/09 version A1.01

MG82FL564 Datasheet
Recommendation MG82FL564 Datasheet
Part MG82FL564
Description 8051-Based MCU
Feature MG82FL564; 8051-Based MCU MG82FE/L564 Data Sheet Version: A1.01 This document contains information on a new p.
Manufacture Megawin
Download MG82FL564 Datasheet

Megawin MG82FL564
MG82FEL564 Data Sheet

Megawin MG82FL564
Enhanced 80C51 Central Processing Unit
64K bytes of MG82Fx564 on-chip flash memory with ISP/IAP capability
ISP memory zone as 1.5KB(default)
Flexible IAP size. 2.5KB(default)
Code protection for flash memory access
Part No.
AP Flash ROM size IAP size
MG82Fx564 60KB (Max.)
2.5KB (Min.)
256 bytes scratch-pad RAM and 1024 bytes expanded RAM (XRAM)
Dual data pointer.
Variable length MOVX for slow SRAM or peripherals.
Three 16-bit timer/counter, Timer 0, Timer 1 and Timer 2.
T0CKO on P34, T1CKO on P35 and T2CKO on P10
X12 mode enabled for T0/T1/T2.
Programmable 16-bit counter/timer Array (PCA) with 6 compare/capture modules
Capture mode
16-bit software timer mode
High speed output mode
8/10/12/16-bit PWM (Pulse Width Modulator) mode with phase shift function
Enhanced UART (S0)
Framing Error Detection
Automatic Address Recognition
a speed improvement mechanism (X2/X4 mode)
Secondary UART (S1)
Dedicated Baud Rate Generator
S1 shares baud rate generator with S0.
Interrupt controller
14 sources, four-level-priority interrupt capability
Four external interrupt inputs, nINT0, nINT1, nINT2 and nINT3.
nINT0/nINT1 trigger type: Low Level or Falling Edge
nINT2/nINT3: Low Level, Falling Edge, High Level or Rising Edge
10-Bit ADC
Programmable throughput up to 200ksps
Up to 8 external inputs (Single-ended)
Master/Slave SPI serial interface
Keypad Interrupt on Port 2
Programmable Watchdog Timer
one time enabled by CPU or power-on.
WDT operating option in MCU power-down.
Maximum 45 GPIOs in LQFP48 package.
P0, P1, P2, P3, P4, P5 can be configured to quasi-bidirectional, push-pull output, open-drain output
and input only
P6.0 and P6.1 serve quasi-bidirectional mode only and shared with XTAL2 and XTAL1
Maximum 41 GPIOs in PQFP44 package.
Two power control modes: idle mode and power-down mode.
All interrupts can wake up IDLE mode.
Four external interrupt and keypad interrupt can wake up Power-Down mode.
Brown-Out Detector: 4.2V for E-series VDD=5V and 2.4V for L-series VDD=3V
Option to reset CPU
Option to interrupt CPU.
MG82FEL564 Data Sheet

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)