16-Bit Microprocessor. UPD8086-2 Datasheet

UPD8086-2 Microprocessor. Datasheet pdf. Equivalent


NEC UPD8086-2
NEe Microcomputers, Inc.
16 BIT MICROPROCESSOR
NEe
JLPD8086
JLPD8086-2'"
DESC RIPT ION
The /lPD8086 is a 16-bit microprocessor that has both 8-bit and 16-bit attributes_ It
has a 16-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz /lPD8085A-2.
FEATU RES
Can Directly Address 1 Megabyte of Memory
• Fourteen 16-Bit Registers with Symmetrical Operations
• Bit, Byte, Word, and Block Operations
• 8 and 16-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal
• Multiply and Divide Instructions
• 24 Operand Addressing Modes
• Assembly Language Compatible with the /lPD8080/8085
• Complet.e Family of Components for Design Flexibility
PIN CONFIGURATION
GND
AD14
AD13
AD12
ADll
AD10
AD9
ADB
AD7
ADS
AD5
AD4
AD3
AD2
ADl
ADO
NMI
INTR
elK
GND
Vee
AD15
A1S/S3
A17/S4
A1B/S5
A19/SS
SHE/S7
MN/MX
RD
HOLD
HlDA
iNA
M/iQ
DTIR
DEN
ALE
INTA
TEST
READY
RESET
(Fffi/GTIi)
(ROIGT1)
(C5CT<)
(82)
(S1)
(Sci)
(OSO)
(OSl)
II
*Preliminary
411


UPD8086-2 Datasheet
Recommendation UPD8086-2 Datasheet
Part UPD8086-2
Description 16-Bit Microprocessor
Feature UPD8086-2; NEe Microcomputers, Inc. 16 BIT MICROPROCESSOR NEe JLPD8086 JLPD8086-2'" DESC RIPT ION The /lPD80.
Manufacture NEC
Datasheet
Download UPD8086-2 Datasheet




NEC UPD8086-2
HPD8086
NO. SYMBOL
NAME
FUNCTION
2·16.39
17
18
19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35-38
26.27.2S
34-38
24.25
29
30.31
ADO-AD15 Address/Data Bus
Multiplexed address IT1) and data (T2. T3. TW. T4) bus.
to8-bit peripherals tied to the lower 8 bits, use AO condition
chip select functions. These lines are tri-state during interrupt
acknowledge and hold states.
NMI
Non-Maskable
Interrupt
This is an edge triggered input causing a type Z interrupt. A
look-up table is used by the processor for vectoring
information.
INTR
ClK
Interrupt Request
Clock
A level triggered input sampled on the last clock cycle of
each instruction. Vectoring is via an interrupt look-up table.
I NTR can mask in software by resetting the interrupt enable
bit.
The clock input is a 1/3 dutY cycle input basic timing for the
processor and bus controller.
RESET
Reset
This active high signal must be high for 4 clock cycles. When
it returns low, the processor restarts execution.
READY Ready
An acknowledgement from memory or I/O that data will be
transferred. Synchroni2ation is done by the p.PD8284 clock
generator.
TEST
Test
This input is examined by the "WAIT" instruction. and if
low, execution continues. Otherwise the processor waits in an
"Idle" state. Synchronized by the processor on the leading
edge of ClK.
iN'i'A
Interrupt
Acknowledge
This is a read strobe for reading vectoring information.
During T2, T3, and TW of each interrupt acknowledge
cycle it is low.
ALE
Address Latch Enable This is used in conjunction with the $£PD8282/8283 latches
to latch the address, during T 1 of any bus cycle.
DEN
Data Enable
This is the output enable for the $£PD8282/8287 transceivers.
It is active low during each memory and I/O access and
INTA cycles.
DTtA
Data Transmit/Receive Used to control the direction of data flow through the
".n~.;v."
MilO
Memory/IO Status
This is used to separate memory access from I/O access.
WR Write
Depending on the state of the MIlO line, the processor is
either writing to 1/0 or memory.
HlDA
Hold Acknowledge
A response to the HOLD input, causing the processor to
tri-state the local bus. The bus return active one cycle after
HO LD goes back low.
HOLD
Hold
When another device requests the local bus. driving HOLD
high, will cause the $£P08086 to issue a HLOA.
Ro Read
Depending on the state of the MIlO line. the processor is
reading from either memory or I/O.
MN/MX
Minimum/Maximum
This input is to tell the processor which mode.it is to be used
iri. This effects some of the pin descriptions.
BRE/S7
Bus/High Enable
This is used in conjunction with the most significant half of
the data bus. Peripheral devices on th is half of the bus use
BHE to condition chip select functions.
A16-A19
Most Significant
Address Bits
The four most significant address bits for memory opera-
tions. Low during I/O operations.
50-57
Status Outputs
These are the status outputs from the processor. They are
used by the p.PD8288 to generate bus control signals.
oS1.QSO Que Status
Used to track the Internal p.PD8086 instruction que.
lOCK
lock
This output is set by the "lOCK" instruction to prevent
other system bus masters from gaining control.
RQ/GTO
ROIGT 1
Req.uest/Grant
Other local bus masters can force the processor to rebase
the local bus at the end of the current bus cycle.
PIN IDENTIFICATION
412



NEC UPD8086-2
BLOCK DIAGRAM
UECUTION UNIT
"EGISTI" FILE
DATA.
POINTE". AND
INDEX "EGS
II WORDSI
IUS INTE"FACE UNIT
I RELOCATION r
MOIaTE" FILE
HOIIENT
"IOISTI"S
AND
INST"UCTION
I'OtNTI"
(I WO"DSI
jLPD8086
,."T ALU
FLAOS
IUS
INTERFACE
UNIT
1H!Is,
A,tIIt
A1~
ADtS-ADo
DTIA,ISIN.ALE
.IYTE
INSTAUCTION
QUEUE
Hft---r------~~------~
INT_
NIIt
AQroTO.,
CONTIlOL • TIlliNG
HOLD
HLDA----~~____r -__~----~--~~
CUt IlIMT "lADy....,... aND
Vee
II
413







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