16-Bit Microprocessor. UPD8086-2 Datasheet
NEe Microcomputers, Inc.
16 BIT MICROPROCESSOR
DESC RIPT ION
The /lPD8086 is a 16-bit microprocessor that has both 8-bit and 16-bit attributes_ It
has a 16-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz /lPD8085A-2.
• Can Directly Address 1 Megabyte of Memory
• Fourteen 16-Bit Registers with Symmetrical Operations
• Bit, Byte, Word, and Block Operations
• 8 and 16-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal
• Multiply and Divide Instructions
• 24 Operand Addressing Modes
• Assembly Language Compatible with the /lPD8080/8085
• Complet.e Family of Components for Design Flexibility
ADO-AD15 Address/Data Bus
Multiplexed address IT1) and data (T2. T3. TW. T4) bus.
to8-bit peripherals tied to the lower 8 bits, use AO condition
chip select functions. These lines are tri-state during interrupt
acknowledge and hold states.
This is an edge triggered input causing a type Z interrupt. A
look-up table is used by the processor for vectoring
A level triggered input sampled on the last clock cycle of
each instruction. Vectoring is via an interrupt look-up table.
I NTR can mask in software by resetting the interrupt enable
The clock input is a 1/3 dutY cycle input basic timing for the
processor and bus controller.
This active high signal must be high for 4 clock cycles. When
it returns low, the processor restarts execution.
An acknowledgement from memory or I/O that data will be
transferred. Synchroni2ation is done by the p.PD8284 clock
This input is examined by the "WAIT" instruction. and if
low, execution continues. Otherwise the processor waits in an
"Idle" state. Synchronized by the processor on the leading
edge of ClK.
This is a read strobe for reading vectoring information.
During T2, T3, and TW of each interrupt acknowledge
cycle it is low.
Address Latch Enable This is used in conjunction with the $£PD8282/8283 latches
to latch the address, during T 1 of any bus cycle.
This is the output enable for the $£PD8282/8287 transceivers.
It is active low during each memory and I/O access and
Data Transmit/Receive Used to control the direction of data flow through the
This is used to separate memory access from I/O access.
Depending on the state of the MIlO line, the processor is
either writing to 1/0 or memory.
A response to the HOLD input, causing the processor to
tri-state the local bus. The bus return active one cycle after
HO LD goes back low.
When another device requests the local bus. driving HOLD
high, will cause the $£P08086 to issue a HLOA.
Depending on the state of the MIlO line. the processor is
reading from either memory or I/O.
This input is to tell the processor which mode.it is to be used
iri. This effects some of the pin descriptions.
This is used in conjunction with the most significant half of
the data bus. Peripheral devices on th is half of the bus use
BHE to condition chip select functions.
The four most significant address bits for memory opera-
tions. Low during I/O operations.
These are the status outputs from the processor. They are
used by the p.PD8288 to generate bus control signals.
oS1.QSO Que Status
Used to track the Internal p.PD8086 instruction que.
This output is set by the "lOCK" instruction to prevent
other system bus masters from gaining control.
Other local bus masters can force the processor to rebase
the local bus at the end of the current bus cycle.
IUS INTE"FACE UNIT
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