AND DRIVER. UPB8224 Datasheet
NEe Microcomputers, Inc.
CLOCK GENERATOR AND DRIVER FOR
DESC RIPT ION
The pPB8224 is a single chip clock generator and driver for 8080A processors.
The clock frequency is determined by a user specified crystal and is capable of
meeting the timing requirements of the entire 8080A family of processors. MOS
and TTL level clock outputs are generated.
Additional logic circuitry of the !1I'B8224 provides signals for power-up reset, an
advance status strobe and properly synchronizes the ready signal to the processor.
This greatly reduces the number of chips needed for 8080A systems.
The !1I'B8224 is fabricated using NEe's Schottky bipolar process.
FE ATU RES
• Crystal Controlled Clocks
• Oscillator Output for External Timing
• MOS Level Clocks for 8080A Processor
• TTL Level Clock for DMA Activities
• Power-up Reset for 8080A Processor
• Ready Synchronization
• Advanced Status Strobe
• Reduces System Package Count
• Available in 16-pin Cerdip and Plastic Packages
The clock generator circuitry consists of a crystal controlled oscillator and a
divide-by-nine counter. The crystal frequency is a function of the SOSOA
processor speed and is basically nine times the processor frequency, i.e.:
Crystal frequency = ~
where tCY is the SOSOA processor clock period.
A series resonant fundamental mode crystal is normally used and is connected
across input pins XTAL 1 and XTAL2. If an overtone mode crystal is used, an
additional LC network, AC coupled to ground, must be connected to the
TANK input of the j.1PBS224 as shown in the followir:g figure.
I I FOR OVERTONE CRYSl ALS ONLY
I l. I
I I (ONLY NEEDED
L _ _ ..I ABOVE 10MHzI
~ _______ ..t~'~3~~~~
FUNCTIONAL DESCR IPTION
The formula for the LC network is:
where F is the desired frequency of oscillation.
The output of the oscillator is input to the divide-by-nine counter. It is also
buffered and brought out on the OSC pin, allowing this stable, crystal controlled
source to be used for derivation of other system timing signals. The divide-by-
nine counter generates the two non-overlapping processor clocks, c;D1 and ¢2,
which are buffered and at MOS levels, a TTL level c;D2 and internal timing signals.
The c;Dl and c;D2 high level outputs are generated in a 2-5-2 digital pattern,with c;Dl
being high for two oscillator periods, <P2 being high for five oscillator periods, and then
neither being high for two oscillator periods. The TTL level <P2,<P2 (TTL), is normally used
for OMA activities by gating the external device onto the SOSOA bus once a Hold
Acknowledge (H LOA) has been issued.
In addition to the clock generator circuitry, the j.1PBS224 contains additional logic
to aid the system designer in the proper timing of several interface signals.
The STSTB signal indicates, at the earliest possible moment, when the status
signals output from the SOSOA processor are stable on the data bus. STSTB is
designed to conneCT directly to the j.1PBS22S System Controller and automatically
resets the j.1PBS22S during power-on Reset.
The R ESI N input to the j.1PBS224 is used to automatically generate a RESET
signal to the SOSOA during power initialization. The slow rise of the power
supply voltage in an external RC network is sensed by an internal Schmitt
Trigger. The output of the Schmitt Trigger is gated to generate an SOSOA com-
patible RESET. An active low manual switch may also be attached to the RC
circuit for manual system reset.
The ROYI N input to the j.1PBS224 accepts an asynchronous "wait request"
and generates a R EAOY output to the SOSOA that is fully synchronized to
meet the SOSOA timing requirements.
Storage Temperature ..
All Output Voltages (TTL) .
All Output Voltages (MOS) .
All Input Voltages ...
Supply Voltage Vee ..
Supply Voltage VOD .. .
Output Currents ... .
...... aOc to +70°C
.. _65°C to +150°C
. . -0.5 to +7 Volts
.. -1.0 to +13.5 Volts
. ...... -1.5 to +7 Volts
-0.5 to +7 Volts
. .............. -0.5 to +13.5 Volts
. . 100 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of .this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
Ta ~ o"c to t70°C. vee" +5V !5%, voo" +12V +5%
Input Current loading
Input leakage Current
Input Forward Clamp Voltage
Input "low . Voltage
Input "High" Voltage
RESIN Input Hysteresis
Output "Low" Voltage
MIN TY. MAX
OutPut "High" Voltage
All Other Outputs
OutPUt Short Circull Current
ISC t.t> -10
(All Low Voltage Outputs Only)
Power Supply Current
Power Supply Current
i l lN o t e '
Caution. 411 and <1>2 outPut dnvers do not have short circuit proteCtion
VF ~ o 45V
VR = 5 2SV
IC - -SmA
VCC = 50V
All Other Inputs
Vce = 5.0V
1('~1. 921, Ready. Reset, STSTB
IOl = 2 5mA
All Other Inputs
IOl = 15mA
'OH = -100 iJA
'OH = -100iJA
IOH = -1 mA
Vo - OV
VCC = 5,OV
Ta "" 25°C; f '" 1 MHz; VCC '" 5V; VDD '" 12V; VBIAS '" 2.5V
Note: G) This parameter is periodically sampled and not 100% tested.