INTERRUPT CONTROLLER. UPD8259A-2 Datasheet

UPD8259A-2 CONTROLLER. Datasheet pdf. Equivalent


NEC UPD8259A-2
NEe Microcomputers, Inc.
NEe
},PD8259A
}'PD8259A-2
PROGRAMMABLE INTERRUPT CONTROLLER
DESC RIPTI ON
The NEC J.lPD8259A is a programmable interrupt controller directly compatible with
the 8080A/8085A/8086/8088 microprocessors. It can service eight levels of interrupts
and contains on-chip logic to expand interrupt capabilities up to 64 levels with the
addition of other J.lPD8259As. The user is offered a selection of priority algorithms to
tailor the priority processing to meet his system requirements. These can be dynami-
cally modified during operation, expanding the versatility of the system.
The J.lPD8259A is completely upward compatible with the J.lPD8259-5, so software
written for the J.lPD8259-5 will run on the J.lPD8259A.
FEATU RES
Eight Level Priority Controller
• Programmable Base Vector Address
• Expandable to 64 Levels
• Programmable Interrupt Modes (Algorithms)
• Individual Request Mask Capability
• Single +5V Supply (No Clocks)
• Full Compatibility with 8080A/8085A/8086/8088
• Available in 28 Pin Plastic and Ceramic Packages
PIN CONFIGURATION cs
WR
AD
07
Os
05
04
03
02
01
DO
CASO
CASl
GNQ
vcc
AO
iNTA
IR7
IRS
IR5
IR4
IR3
IR2
IR1
IRO
INT
SP/EN
CAS 2
07 - DO
RD
WR
AO
CAS2- CASO
SP/EN
INT
INTA
IRO-IR7
~
PIN NAMES
Data Bus (Bi-Directional)
Read Input
Write Input
Command Select Address
Cascade Lines
Slave Program Input I
Enable Buffer
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Chip Select
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UPD8259A-2 Datasheet
Recommendation UPD8259A-2 Datasheet
Part UPD8259A-2
Description PROGRAMMABLE INTERRUPT CONTROLLER
Feature UPD8259A-2; NEe Microcomputers, Inc. NEe },PD8259A }'PD8259A-2 PROGRAMMABLE INTERRUPT CONTROLLER DESC RIPTI O.
Manufacture NEC
Datasheet
Download UPD8259A-2 Datasheet




NEC UPD8259A-2
p.PD8259A
BLOCK DIAGRAM
AO
PROCESSOR PROCESSOR PROCESSOR
ADDRESS CONTROL
DATA
BUS
BUS
BUS
PROGRAM
ENABLE
INTERNAL
eus
Operating Temperature ....
Storage Temperature ..
Voltage on Any Pin ..
Power Dissipation ....
CDNote: With respect to ground.
. . . . . . .. O°C to +70°C
..... -65°C to +150oC
CD-0.5 to +7 Volts
lW
ABSOLUTE MAXIMUM
RATINGS*
COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
642



NEC UPD8259A-2
DC CHARACTERISTICS
JLPD8259A
Ta =o·c to 70·C; VCC=+5V ± 10%
PARAMETER
SYMBOL MIN
LIMITS
TYP
MAX
UNIT
TEST
CONDITIONS
Input Low Voltage
Input High Voltage'
Output Low Voltage
Output High Voltage
Interrupt Output-
High Voltage
Input Leakage Current
for IRO_7
Input Leakage Current
for other Inputs
Output Leakage Current
Output Leakage Current
v CC Supply Current
VIL
VIH
VOL
VOH
VOH-INT
IllIIR O_7 '
III
IlOl
IlOH
ICC
-0.5
2.0
2.4
2.4
3.5
0.8 V
Vee + 0.5V
V
0.45
V IOl = 2mA
V IOH = -400 ~A
V IOH = -400 ~A
V IOH - -50~A
-300
10
~A VIN = OV
~A VIN-Vee
10 ~A VIN = Vce to OV
- 10
10
100
"A VOUT = 0.45 V
"A VOUT = Vee
mA
CAPACITANCE Ta = 25°C; VCC =GND =OV
PARAMETER
Input Capac itance
I/O Capacitance
SYMBOL
CIN
CliO
LIMITS
MIN TYP MAX
10
20
UNIT
pF
pF
TEST
CONDITIONS
fc = 1 MHz
Unmeasured Pins
Returned to VSS
AC CHARACTE RISTI CS
T,.O°Cto 70°C;Vcc' 5V ± 10% i.PD8259AJ
PARAMETER
SYMBOL
.PD8259A .PD8269A-2
MIN MAX MIN MAX UNIT
AO/CS Setup to RD/lNTA./.
AO/CS Hold after RD/INTAt
RD Pulse Width
AO/CS Setup to WR./.
AO/CS Hold after WR t
WR Pulse Width
Data Setup to WR t
Data Hold after WR t
Interrupt Request Width (Low)
Cascade Setup to Second or Third
iNTA t (Slave Only)
End of RD to Next Command
End of WR to Next Command
tAHRL
tRHAX
tRLRH
tAHWL
tWHAX
'WLWH
tOVWH
tWHDX
tJUH
tCVIAL
tRHRL
tWHRL
0
0
235
0
0
290
240
0
100
66
160
190
0
0
160
0
0
190
160
0
100
40
160
190
ns
ns
n,
ns
ns
ns
ns
ns
ns
ns
ns
ns
CDNote: This is the low time required to clear the input latch in the edge triggered mode.
TEST
CONDITIONS
CD
PARAMETER
Data Valid from RD/INTA.!.
Data Float after RD/i"N'TAt
Interrupt Output Delay
Cascade Valid from First INTAJ.
(Master Only)
Enable Active from AD", or INTA.!.
Enable Inactive from ROt or INTAt
Data Valid from Stable Address
Cascade Valid to Valid Data
SYMBOL
tRLDV
tRHoZ
tJHIH
IIA'HCV
tALEL
tRHEH
tAHoV
tCVoV
.uP08259A • PD8259A-2
MIN MAX MIN MAX UNIT
TEST
CONDITIONS
200 120 ns C uf Data Bus = 100 pF
C Df Data Bus
100 85 n, M.M Test C = 100 pF
Min TltSt C "" 15 pF
350 300 ns
565 360 ns CINf .. 100pF
125 100 ns CCASCADE = 100 pF
150 150 ns
200 200 ns
300 200 ns
II
643







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