UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMITTER. ST16C2450 Datasheet

ST16C2450 ASYNCHRONOUSRECEIVER/TRANSMITTER. Datasheet pdf. Equivalent


STARTECH ST16C2450
STARTECH
ST16C2450
An Company
Printed June 19, 1996
DUAL UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMITTER
DESCRIPTION
The ST16C2450 is a dual universal asynchronous
receiver and transmitter. Independent programmable
baud rate generators are provided to select transmit
and receive clock rates from 50Hz to 1.5 MHz for each
UART section.
The ST16C2450 is an improved version of the
NS16C450 UART with higher operating speed and
lower access time. The ST16C2450 on board status
registers provides the error conditions, type and
status of the transfer operation being performed.
Included is complete MODEM control capability, and
a processor interrupt system that may be software
tailored to the user’s requirements. The ST16C2450
provides internal loop-back capability for on board
diagnostic testing.
The ST16C2450 is fabricated in an advanced 1.2m
CMOS process to achieve low drain power and high
speed requirements.
PLCC Package
D5 7
D6 8
D7 9
RXB 10
RXA 11
N.C. 12
TXA 13
TXB 14
OPB* 15
CSA* 16
CSB* 17
ST16C2450CJ44
39 RESET
38 DTRB*
37 DTRA*
36 RTSA*
35 OPA*
34 N.C.
33 INTA
32 INTB
31 A0
30 A1
29 A2
Plastic-DIP Package
FEATURES
· Functional compatible to NS16450, VL16C450,
WD16C450
· Modem control signals (CTS*, RTS*, DSR*, DTR*,
RI*, CD*)
· Programmable character lengths (5, 6, 7, 8)
· Even, odd, or no parity bit generation and detection
· Status report register
· Independent transmit and receive control
· TTL compatible inputs, outputs
· 460.8 kHz transmit/receive operation with 7.372
MHz crystal or external clock source
ORDERING INFORMATION
Part number
Package Operating temperature
ST16C2450CP40 Plastic-DIP 0° C to + 70° C
ST16C2450CJ44 PLCC
0° C to + 70° C
*Industrial operating range are available
Rev. 2.1
3-21
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
RXB 9
RXA 10
TXA 11
TXB 12
OPB* 13
CSA* 14
CSB* 15
XTAL1 16
XTAL2 17
IOW* 18
CDB* 19
GND 20
40 VCC
39 RIA*
38 CDA*
37 DSRA*
36 CTSA*
35 RESET
34 DTRB*
33 DTRA*
32 RTSA*
31 OPA*
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 CTSB*
24 RTSB*
23 RIB*
22 DSRB*
21 IOR*


ST16C2450 Datasheet
Recommendation ST16C2450 Datasheet
Part ST16C2450
Description DUAL UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMITTER
Feature ST16C2450; STARTECH ST16C2450 An Company Printed June 19, 1996 DUAL UNIVERSAL ASYNCHRONOUSRECEIVER/TRANSMIT.
Manufacture STARTECH
Datasheet
Download ST16C2450 Datasheet




STARTECH ST16C2450
ST16C2450
BLOCK DIAGRAM
D0-D7
IOR*
IOW*
RESET
A0-A2
CSA*
CSB*
INTA
INTB
Transmit
Holding
Register
Transmit
Shift
Register
TX A/B
Receive
Holding
Register
Receive
Shift
Register
RX A/B
Clock
&
Baud Rate
Generator
Modem
Control
Logic
DTR A/B*
RTS A/B*
OP A/B*
CTS A/B*
RI A/B*
CD A/B*
DSR A/B*
3-22



STARTECH ST16C2450
ST16C2450
SYMBOL DESCRIPTION
Symbol
D0-D7
RX A/B
TX A/B
CS* A/B
XTAL1
XTAL2
IOW*
IOR*
A0-A2
INT A/B
Pin
40 44
1-8 2-9
Signal Type
Pin Description
I/O Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. D0 is the least
significant bit of the data bus and the first serial data bit to
be received or transmitted.
10,9 11,10 I Serial data input A/B. The serial information (data) received
from serial port to ST16C2450 receive input circuit. A mark
(high) is logic one and a space (low) is logic zero. During the
local loopback mode the RX input is disabled from external
connection and connected to the TX output internally.
11,12 13,14
O
Serial data output A/B. The serial data is transmitted via
this pin with additional start , stop and parity bits. The TX will
be held in mark (high) state during reset, local loopback
mode or when the transmitter is disabled.
14,15 16,17
I
Chip select A/B. (active low) A low at this pin enables the
ST16C2450 / CPU data transfer operation.
16 18
I Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internal circuit and baud rate generator for custom transmis-
sion rates.
17 19
O Crystal input 2 or buffered clock output. See XTAL1.
18 20
I Write strobe. (active low) A low on this pin will transfer the
contents of the CPU data bus to the addressed register.
21 24
I Read strobe. (active low) A low level on this pin transfers
the contents of the ST16C2450 data bus to the CPU.
28-26 31-29
I
Address select lines. To select internal registers.
30,29 33,32
O
Interrupt output A/B. (active high) This pin goes high (when
enabled by the interrupt enable register) whenever a re-
ceiver error, receiver data available, transmitter empty, or
modem status condition flag is detected.
3-23







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)