Audio DSP. AK7780 Datasheet

AK7780 DSP. Datasheet pdf. Equivalent

AK7780 Datasheet
Recommendation AK7780 Datasheet
Part AK7780
Description 24bit 5ch ADC & SRC + Audio DSP
Feature AK7780; [AK7780] AK7780 24bit 5ch ADC & SRC + Audio DSP GENERAL DESCRIPTION The AK7780 is a highly integrate.
Manufacture AKM
Datasheet
Download AK7780 Datasheet




AKM AK7780
[AK7780]
AK7780
24bit 5ch ADC & SRC + Audio DSP
GENERAL DESCRIPTION
The AK7780 is a highly integrated audio processor, including a 28-bit floating point DSP, two 24-bit stereo
ADC’s and one mono ADC. The stereo ADC’s feature high performance, achieving 96dB dynamic range,
they include 8:1 input selectors. The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The
AK7780 also includes a stereo sample rate converter (SRC), so it can be used as a master device when
it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable
for creating simulated surround fields. The programmable DSP block is realized with 2560step/fs DSP. It
supports sampling frequencies from 7.35kHz to 96 kHz. The AK7780 is used to implement complete
sound field control, such as echo, 3D, parametric equalization, and other sound enhancements. It is
packaged in a 100-lead LQFP package.
FEATURES
[DSP]
Main
„ Word length: 28-bit (Data RAM F24.4 limited range floating point)
„ Instruction cycle time: 8.1 ns (2560step/fs fs=48kHz; 1280step/fs fs=96kHz)
„ Multiplier: 24 x 16 40-bit (Double precision available)
„ Divider: 24 / 24 24-bit
„ ALU: 44-bit arithmetic operation (overflow margin: 4-bits)
F24.4 arithmetic and logic operation
„ Shift+Register: Flexible setting
„ Program RAM: 2048 x 36-bit
„ Coefficient RAM: 2048 x 16-bit
„ Data RAM: 2048 x 28-bit (F24.4[sign bit + 23-bit mantissa + 4-bit exponent])
„ Offset RAM: 64 x 13-bit
„ Internal Delay RAM: 168kbits
( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit
/ 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting
28bit = F24.4 [24 bit sign & mantissa: 4 bit exponent]
14bit = F10.4 [10 bit sign & mantissa: 4 bit exponent]
„ Sampling frequency: 7.35kHz ~ 96kHz
„ Serial interface port for microcontroller or I2C BUS control
„ Master Clock: 2560fs (generated by PLL from 32fs ,64fs, 256fs and 384fs)
„ Master/Slave operation
„ Serial signal input port (10ch): MSB justified 24-bit / LSB justified 16/20/24-bit and I2S
„ Serial signal output port(12ch): MSB justified 24-bit / LSB justified 24,16-bit and I2S
(SDOUT1,SDOUT2 and SDOUT3)
[ADC]
4 channels (2 stereo pairs)
„ 24-bit 64X over-sampling delta-sigma (fs = 7.35kHz ~ 96kHz)
„ DR, S/N: 96dBA (fs = 48kHz, fully-differential input)
„ S/(N+D): 92dB (fs = 48kHz)
„ Digital HPF (fc = 1Hz)
MS0581-E-00-PB
-1-
2007/09



AKM AK7780
[ADC]
Mono single channel
„ 24-bit 64X over-sampling delta sigma (fs = 7.35kHz ~ 96kHz)
„ DR, S/N: 95dBA ( fs = 48kHz)
„ Includes digital attenuator
[SRC]
Stereo pair
„ Input frequency 7.35kHz ~ 96kHz Output frequency 44.1kHz ~ 96kHz
[Other]
„ Power supply: +3.3V ±0.3V, +1.7V~+2.0V(typ +1.8V)
„ Operating temperature range: -40°C~85°C
„ Package: 100pin LQFP(0.5mm pitch)
[AK7780]
MS0581-E-00-PB
-2-
2007/09



AKM AK7780
BLOCK DIAGRAM
[AK7780]
4 2 222222
pull down
Hi-z
I/O
SDIN5
SDIN4
SDIN3
SDIN2
SDIN1
ADC1
ADC2
SELI5
SELI4
SELI3
SELI1
SDIN6
SDIN5
SDIN4
SDIN3
SDIN2
SDIN1
ADCM
ctrl reg sw
VREF
VOL
SDOUT6
SDOUT5
SDOUT4
SDOUT3
SDOUT2
SDOUT1
IRPT
GPO1
GPO0
MUX
SELOA1[1:0]
0
OUTA1E_
1N
2
3
SELOA2[1:0]
0
1
2
3
SEL_SDO6
SWIRP
T
OUT6E_
N
SWG1 OUT5E_
N
OUT4E_
SWG0 N
OUT3E_
N
OUT2E_
N
OUT1E_
N
MICIF
SEL_SDO2
SEL_SDO1
P_SRCSMUTE
P_SRCRST
SRC_LRCK
SRC_BICK
R_SRCSMUTE
R_SRCRST_N
SRCSET[1]
SRCSET[0]
SRC_LFLT
TESTO
LRCLK_O
BITCLK_O
TESTI2
TESTI1
CKM[2:0] 3
P_CKRST R_CKRST_N
P_DSPRST
P_ADRST
R_DSPRST_N
R_ADRST_N
INIT_RESET
SRCI
SRCOUT
SRC
UNLOCK
CKRST_N
DSPRST_N
S_RESET_N
ADRST_N
DSP
JX2
JX1
JX0
WDT
CRC
WDTE_N
CRC_E
LOCK_E
CONTROLLER
(Master="H",Slave="L")
SMODE
CLKO2E_N
CLKO1E_N
LRCLK_I BITCLK_I LFLT
3 AVDD
VREFH
VCOM
VREFL
3 AVSS
SDOUTA1
SDOUT6
SDOUT5
SDOUT4
SDOUT3
SDOUT2
SDOUT1
I2CSEL
RQ_N/CAD1
SCLK/SCL
SI/CAD0
SO
SDA
RDY
JX2
JX1
JX0
STO
XTI
XTO
CLKO2
CLKO1
2 BVSS
7 DVDD18
83 DVSS
63 DVDD
Figure 1. Whole Block Diagram
* Figure 1 shows a simplified diagram of the AK7780, which isn’t the perfect same as the actual circuit diagram.
Each \ describes the relationship of reset control and target reset blocks.
MS0581-E-00-PB
-3-
2007/09







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