Document
Data Sheet
Dual, 16-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface
AD5689R/AD5687R
INTERFACE LOGIC
11256-001
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP TUE: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range AEC-Q100 qualified for automotive applications
APPLICATIONS
Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems
GENERAL DESCRIPTION
The AD5689R/AD5687R members of the nanoDAC+™ family are low power, dual, 16-/12-bit buffered voltage output digital-to-analog converters (DACs). The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. Both devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.
The AD5689R/AD5687R also incorporate a power-on reset circuit and a RSTSEL pin that ensure that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.
The AD5689R/AD5687R use a versatile serial peripheral interface (SPI) that operates at clock rates up to 50 MHz. Both devices contain a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.
VLOGIC SCLK SYNC SDIN
SDO
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5689R/AD5687R
2.5V REFERENCE
INPUT REGISTER
DAC REGISTER
STRING DAC A
INPUT REGISTER
DAC REGISTER
STRING DAC B
BUFFER BUFFER
VOUT A VOUT B
LDAC RESET
POWER-ON RESET
GAIN = ×1/×2
RSTSEL
Figure 1.
GAIN
POWERDOWN LOGIC
Table 1. Dual nanoDAC+ Devices
Interface
Reference
16-Bit
SPI
Internal
AD5689R
External
AD5689
I2C Internal
12-Bit AD5687R AD5687 AD5697R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL). AD5689R (16-bit): ±2 LSB maximum AD5687R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient
3. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP
Rev. C
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AD5689R/AD5687R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Daisy-Chain and Readback Timing Characteristics ............... 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 19 Digital-to-A.