Microwave Upconverter. ADRF6780 Datasheet

ADRF6780 Upconverter. Datasheet pdf. Equivalent

ADRF6780 Datasheet
Recommendation ADRF6780 Datasheet
Part ADRF6780
Description Microwave Upconverter
Feature ADRF6780; Data Sheet 5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter ADRF6780 FEATURES GENERAL DESCRIP.
Manufacture Analog Devices
Datasheet
Download ADRF6780 Datasheet




Analog Devices ADRF6780
Data Sheet
5.9 GHz to 23.6 GHz,
Wideband, Microwave Upconverter
ADRF6780
FEATURES
GENERAL DESCRIPTION
Wideband RF output frequency range: 5.9 GHz to 23.6 GHz
Two upconversion modes
Direct conversion from baseband I/Q to RF
Single sideband upconversion from real IF
LO input frequency range: 5.4 GHz to 14 GHz
LO doubler for up to 28 GHz
Matched 100 Ω balanced RF output, LO input, and IF input
High impedance baseband inputs
Sideband suppression and carrier feedthrough optimization
Variable attenuator and power detector for Tx power control
Programmable via 4-wire SPI interface
32-lead, 5 mm × 5 mm LFCSP microwave packaging
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
Instrumentation, automatic test equipment (ATE)
The ADRF6780 is a silicon germanium (SiGe) design, wideband,
microwave upconverter optimized for point to point microwave
radio designs operating in the 5.9 GHz to 23.6 GHz frequency
range.
The upconverter offers two modes of frequency translation. The
device is capable of direct conversion to radio frequency (RF)
from baseband I/Q input signals, as well as single sideband (SSB)
upconversion from a real intermediate frequency (IF) input
carrier frequency. The baseband inputs are high impedance and
are generally terminated off chip with 100 Ω differential back
terminations. The baseband I/Q input path can be disabled and
a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can
fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz
while suppressing the unwanted sideband by typically better than
25 dBc. The serial port interface (SPI) allows tweaking of the
quadrature phase adjustment to allow optimum sideband
suppression. In addition, the SPI interface allows powering down
the output power detector to reduce power consumption when
power monitoring is not necessary.
The ADRF6780 upconverter comes in a compact, thermally
enhanced, 5 mm × 5 mm LFCSP package. The ADRF6780
operates over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
ALM VPLO LOIP AGND LOIN VPLO SEN SDTO
32 31 30 29 28 27 26 25
VDET 1
ADC
SPI 24 SCLK
VPDT 2
VPRF 3
LOG
DET
×1 ×2
BIAS
CONTROL
23 SDIN
22 VP18
AGND 4
21 VPBI
RFOP 5
AGND 6
VVA
QUAD
SPLITTER
BUFFER
20 IFIP
19 AGND
RFON 7
18 IFIN
AGND 8
ADRF6780 17 RST
9
VPRF
10
VATT
11
BBQN
12 13
BBQP BBIP
Figure 1.
14 15 16
BBIN VPBB PWDN
Rev. D
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Analog Devices ADRF6780
ADRF6780
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
I/Q Mode ....................................................................................... 9
IF Mode........................................................................................ 14
Output Detector Performance .................................................. 19
Return Loss.................................................................................. 20
Theory of Operation ...................................................................... 21
Baseband...................................................................................... 21
Single Sideband (SSB) Upconversion ...................................... 21
LO Input Path.............................................................................. 21
Serial Port Interface (SPI).......................................................... 21
Applications Information .............................................................. 23
Carrier Feedthrough Nulling.................................................... 23
Sideband Suppression Optimization ....................................... 23
Linearity....................................................................................... 23
ADC ............................................................................................. 23
Wide Frequency Performance .................................................. 24
Layout .......................................................................................... 24
LO Input Driven Differential vs. Single Ended .......................... 25
Register Summary .......................................................................... 27
Register Details: Wideband Upconverter.................................... 28
Control Register ......................................................................... 28
ALARM_READBACK Register ............................................... 28
ALARM_MASK Register .......................................................... 29
Enable Register ........................................................................... 29
Linearize Register....................................................................... 30
LO_PATH Register..................................................................... 30
ADC_CONTROL Register ....................................................... 31
ADC_OUTPUT Register .......................................................... 31
Basic Connections for Operation................................................. 32
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
1/2019—Rev. C to Rev. D
Changes to ADC Section............................................................... 23
7/2018—Rev. B to Rev. C
Changed 32.95 to 9.18 in θJA Column, Table 3 ............................. 6
Changes to Ordering Guide .......................................................... 35
10/2017—Rev. A to Rev. B
Changes to Maximum Junction Temperature Parameter, Table 2... 6
Change to Table 4 ......................................................................................... 7
Changes to Figure 31 Caption.................................................................13
Changes to Ordering Guide.....................................................................35
5/2016—Rev. 0 to Rev. A
Change to Table 4 ............................................................................. 7
Changes to Figure 40...................................................................... 15
Changes to Figure 47...................................................................... 16
Changes to Figure 58...................................................................... 18
Change to Figure 84 ....................................................................... 33
Changes to Table 16........................................................................ 34
3/2016—Revision 0: Initial Version
Rev. D | Page 2 of 35



Analog Devices ADRF6780
Data Sheet
ADRF6780
SPECIFICATIONS
VPBB = VPBI = VPLO = 3.3 V, VP18 = 1.8 V, VPDT = VPRF = 5 V, TA = 25°C, LO = 0 dBm differential drive; baseband I/Q amplitude =
−15 dBm differential sine waves in quadrature with a 500 mV dc bias, baseband input termination with 100 Ω externally, IF amplitude =
−12 dBm differential sine waves, unless otherwise noted.
Table 1.
Parameter
RF OUTPUT FREQUENCY RANGE
LOCAL OSCILLATOR (LO) INPUT
FREQUENCY RANGE
LO AMPLITUDE RANGE
IF INPUT FREQUENCY RANGE
BASEBAND (BB) I/Q INPUT FREQUENCY
RANGE
I/Q MODULATOR PERFORMANCE
Modulator Voltage Gain
Output Noise Density
Output Third-Order Intercept (OIP3)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
Fifth-Order Intermodulation Distortion
(IMD5)
Output Second-Order Intercept (OIP2)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
Output 1 dB Compression Point (P1dB)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
LO Feedthrough
Sideband Suppression
Test Conditions/Comments
Min
5.9
5.4
−6
0.8
DC
Maximum gain at maximum gain setting
Minimum gain at minimum gain setting
Output carrier > −5 dBm
Output carrier > −14 dBm
Output carrier > −22.5 dBm
f1BB = 10 MHz, f2BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
10
f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting (can be improved baseband dc
offset adjustment)
At 10 dB gain setting
Typ Max Unit
23.6 GHz
14 GHz
0 +6 dBm
3.5 GHz
750 MHz
13
−12
−147
−145
−136
dB
dB
dBc/Hz
dBc/Hz
dBc/Hz
24 dBm
25 dBm
27 dBm
27 dBm
65 dBm
65 dBm
65 dBm
66 dBm
50 dBm
10.5 dBm
11 dBm
11 dBm
12 dBm
10 dBm
12 dBm
10 dBm
11 dBm
−25 dBm
25 dBc
Rev. D | Page 3 of 35







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