Jitter Attenuator. HMC7044 Datasheet

HMC7044 Attenuator. Datasheet pdf. Equivalent

HMC7044 Datasheet
Recommendation HMC7044 Datasheet
Part HMC7044
Description 14-Output Jitter Attenuator
Feature HMC7044; Data Sheet High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B HMC7044 FEATURES U.
Manufacture Analog Devices
Datasheet
Download HMC7044 Datasheet




Analog Devices HMC7044
Data Sheet
High Performance, 3.2 GHz, 14-Output
Jitter Attenuator with JESD204B
HMC7044
FEATURES
Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at
2457.6 MHz
Noise floor: −156 dBc/Hz at 2457.6 MHz
Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
from PLL2
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency up to 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog, and ½ VCO cycle digital delay independently
programmable on each of 14 clock output channels
SPI-programmable phase noise vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Narrow-band, dual core VCOs
Up to 2 buffered voltage controlled oscillator (VCXO) outputs
Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
Frequency holdover mode to maintain output frequency
Loss of signal (LOS) detection and hitless reference switching
4× GPIOs alarms/status indicators to determine the health of
the system
External VCO input to support up to 6000 MHz
On-board regulators for excellent PSRR
68-lead, 10 mm × 10 mm LFCSP package
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Microwave baseband cards
Phase array reference distribution
GENERAL DESCRIPTION
The HMC7044 is a high performance, dual-loop, integer-N
jitter attenuator capable of performing reference selection and
generation of ultralow phase noise frequencies for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7044 features two integer mode PLLs and overlapping
on-chip VCOs that are SPI-selectable with wide tuning ranges
around 2.5 GHz and 3 GHz, respectively. The device is designed
to meet the requirements of GSM and LTE base station designs,
and offers a wide range of clock management and distribution
features to simplify baseband and radio card clock tree designs.
The HMC7044 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different compo-
nents including data converters, field-programmable gate arrays
(FPGAs), and mixer local oscillators (LOs).
The DCLK and SYSREF clock outputs of the HMC7044 can be
configured to support signaling standards, such as CML, LVDS,
LVPECL, and LVCMOS, and different bias settings to offset
varying board insertion losses.
FUNCTIONAL BLOCK DIAGRAM
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
CLKIN1/FIN
CLKIN1/FIN
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
CLKIN3
CLKIN3
SYNC
SDATA
OSCIN
CPOUT1 OSCIN
CPOUT2 OSCOUT1 OSCOUT1
PLL1
PLL2
÷
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
SPI
CONTROL
INTERFACE
SYSREF
CONTROL
÷
14-CLOCK
DISTRIBUTION
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SLEN SCLK
Figure 1.
Rev. B
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HMC7044* PRODUCT PAGE QUICK LINKS
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COMPARABLE PARTS
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EVALUATION KITS
HMC7044 Evaluation Kit
DOCUMENTATION
Data Sheet
HMC7044: High Performance, 3.2 GHz, 14-Output Jitter
Attenuator with JESD204B Data Sheet
User Guides
UG-826: Evaluating the HMC7044 Dual Loop Clock Jitter
Cleaner
TOOLS AND SIMULATIONS
HMC7044 IBIS Model
REFERENCE MATERIALS
Press
Analog Devices Clock Jitter Attenuator Optimizes
JESD204B Serial Interface Functionality in Base Station
Designs
Technical Articles
Synchronizing Sample Clocks of a Data Converter Array
DESIGN RESOURCES
HMC7044 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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Analog Devices HMC7044
HMC7044
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Table of Contents .............................................................................. 2
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Conditions ..................................................................................... 3
Supply Current.............................................................................. 3
Digital Input/Output (I/O) Electrical Specifications............... 4
PLL1 Characteristics .................................................................... 5
PLL2 Characteristics .................................................................... 7
VCO Characteristics .................................................................... 8
Clock Output Distribution Characteristics............................... 9
Spur Characteristics ................................................................... 10
Noise and Jitter Characteristics ................................................ 10
Clock Output Driver Characteristics....................................... 11
Absolute Maximum Ratings.......................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 17
Typical Application Circuits.......................................................... 21
Terminology .................................................................................... 22
REVISION HISTORY
11/2016—Rev. A to Rev. B
Changes to Table 1 and Endnote 4, Table 2................................... 3
Changes to Reliable Signal Swing Parameter, Table 4.................. 5
Change to PLL2 VCXO Input Parameter, Table 5........................ 7
Changes to Table 7............................................................................ 9
Added Figure 13; Renumbered Sequentially .............................. 18
Added Figure 20.............................................................................. 19
Added Figure 21, Figure 22, and Figure 23 ................................. 20
Changes to Figure 34...................................................................... 21
Changes to Table 15 and Table 17 ................................................ 34
Changes to Figure 47...................................................................... 37
Changes to Table 23........................................................................ 41
Changes to Table 25........................................................................ 46
Changes to Table 49........................................................................ 57
Change to Table 75 ......................................................................... 68
Data Sheet
Theory of Operation ...................................................................... 23
Detailed Block Diagram ............................................................ 24
Dual PLL Overview.................................................................... 25
Component Blocks—Input PLL (PLL1).................................. 25
Component Blocks—Output PLL (PLL2) .............................. 30
Clock Output Network .............................................................. 31
Reference Buffer Details ............................................................ 38
Typical Programming Sequence............................................... 38
Power Supply Considerations ................................................... 39
SeriaL Control Port ........................................................................ 42
Serial Port Interface (SPI) Control........................................... 42
Applications Information .............................................................. 43
PLL1 Noise Calculations ........................................................... 43
PLL2 Noise Calculations ........................................................... 43
Phase Noise Floor and Jitter...................................................... 43
Control Registers ............................................................................ 44
Control Register Map ................................................................ 44
Control Register Map Bit Descriptions ................................... 52
Evaluation PCB Schematic............................................................ 69
Evaluation PCB........................................................................... 69
Outline Dimensions ....................................................................... 71
Ordering Guide .......................................................................... 71
5/2016—Rev. 0 to Rev. A
Changes to Table 3.............................................................................4
Changes to Current Range (ICP2) Parameter, Table 5 ....................8
Changes to Table 9.......................................................................... 11
Changes to Table 10 ....................................................................... 13
Changes to LDOBYP5 Pin Description ...................................... 15
Changes to Figure 13...................................................................... 19
Changes to Figure 30...................................................................... 25
Changes to Evaluation PCB Section ............................................ 69
Added Figure 46; Renumbered Sequentially .............................. 69
Added Figure 50 ............................................................................. 71
Updated Outline Dimensions....................................................... 71
9/2015—Revision 0: Initial Version
Rev. B | Page 2 of 72







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