Clock Generator. AD9528 Datasheet

AD9528 Generator. Datasheet pdf. Equivalent

AD9528 Datasheet
Recommendation AD9528 Datasheet
Part AD9528
Description JESD204B Clock Generator
Feature AD9528; Data Sheet JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 FEATURES 14 outputs configura.
Manufacture Analog Devices
Datasheet
Download AD9528 Datasheet




Analog Devices AD9528
Data Sheet
JESD204B Clock Generator with
14 LVDS/HSTL Outputs
AD9528
FEATURES
14 outputs configurable for HSTL or LVDS
Maximum output frequency
6 outputs up to 1.25 GHz
8 outputs up to 1 GHz
Dependent on the voltage controlled crystal oscillator
(VCXO) frequency accuracy (start-up frequency accuracy:
<±100 ppm)
Dedicated 8-bit dividers on each output
Coarse delay: 63 steps at 1/2 the period of the RF VCO
divider output frequency with no jitter impact
Fine delay: 15 steps of 31 ps resolution
Typical output to output skew: 20 ps
Duty cycle correction for odd divider settings
Output 12 and Output 13, VCXO output at power-up
Absolute output jitter: <160 fs at 122.88 MHz, 12 kHz to
20 MHz integration range
Digital frequency lock detect
SPI- and I2C-compatible serial control port
Dual PLL architecture
PLL1
Provides reference input clock cleanup with external VCXO
Phase detector rate up to 110 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVDS/HSTL outputs from VCXO used for radio
frequency/intermediate frequency (RF/IF) synthesizers
PLL2
Phase detector rate of up to 275 MHz
Integrated low noise VCO
APPLICATIONS
High performance wireless transceivers
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs;
supports JESD204B
Low jitter, low phase noise clock distribution
ATE and high performance instrumentation
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VXCO_IN
REFA
REFB
REF_SEL
PLL1
PLL2
SYSREF_REQ
SYSREF
JESD204B
֯
֯
OUT0/
OUT0
OUT13/
OUT13
CONTROL
INTERFACE
(SPI AND I2C)
AD9528
CLOCK
DISTRIBUTION
14 OUTPUTS
Figure 1.
GENERAL DESCRIPTION
The AD9528 is a two-stage PLL with an integrated JESD204B
SYSREF generator for multiple device synchronization. The
first stage phase-locked loop (PLL) (PLL1) provides input
reference conditioning by reducing the jitter present on a
system clock. The second stage PLL (PLL2) provides high
frequency clocks that achieve low integrated jitter as well as low
broadband noise from the clock output drivers. The external
VCXO provides the low noise reference required by PLL2 to
achieve the restrictive phase noise and jitter requirements
necessary to achieve acceptable performance. The on-chip VCO
tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF
generator outputs single shot, N-shot, or continuous signals
synchronous to the PLL1 and PLL2 outputs to time align
multiple devices.
The AD9528 generates six outputs (Output 0 to Output 3,
Output 12, and Output 13) with a maximum frequency of
1.25 GHz, and eight outputs with a maximum frequency of up
to 1 GHz. Each output can be configured to output directly
from PLL1, PLL2, or the internal SYSREF generator. Each of
the 14 output channels contains a divider with coarse digital
phase adjustment and an analog fine phase delay block that
allows complete flexibility in timing alignment across all 14
outputs. The AD9528 can also be used as a dual input flexible
buffer to distribute 14 device clock and/or SYSREF signals. At
power-up, the AD9528 sends the VCXO signal directly to
Output 12 and Output 13 to serve as the power-up ready
clocks.
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function where applicable.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com



Analog Devices AD9528
AD9528
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications .................................................................................... 4
Conditions..................................................................................... 4
Supply Current ............................................................................. 4
Power Dissipation ........................................................................ 5
Input Characteristics—REFA, REFA, REFB, REFB,
VCXO_IN, VCXO_IN, SYSREF_IN, and SYSREF_IN.......... 6
PLL1 Characteristics .................................................................... 6
VCXO_VT Output Characteristics ........................................... 7
PLL2 Characteristics .................................................................... 7
Clock Distribution Output Characteristics .............................. 7
Output Timing Alignment Characteristics .............................. 8
SYSREF_IN, SYSREF_IN, VCXO_IN, and VCXO_IN
Timing Characteristics ................................................................ 8
Clock Output Absolute Phase Noise—Dual Loop Mode ....... 9
Clock Output Absolute Phase Noise—Single Loop Mode ... 10
Clock Output Absolute Time Jitter ......................................... 11
Clock Output Additive Time Jitter (Buffer Mode)................ 12
Logic Input Pins—RESET, REF_SEL, and SYSREF_REQ ... 12
Status Output Pins—STATUS0 and STATUS1..................... 12
Serial Control Port—Serial Port Interface (SPI) Mode......... 13
Serial Control Port—I2C Mode ................................................ 14
Absolute Maximum Ratings ......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions .......................... 16
Typical Performance Characteristics........................................... 19
Input/Output Termination Recommendations ......................... 22
Typical Application Circuit .......................................................... 23
Terminology.................................................................................... 24
Data Sheet
Theory of Operation ...................................................................... 25
Detailed Block Diagram ............................................................ 25
Overview...................................................................................... 25
Component Blocks—PLL1 ....................................................... 26
Component Blocks—PLL2 ....................................................... 27
Clock Distribution ..................................................................... 29
SYSREF Operation ......................................................................... 32
SYSREF Signal Path ................................................................... 32
SYSREF Generator ..................................................................... 34
Serial Control Port ......................................................................... 35
SPI/I2C Port Selection................................................................ 35
SPI Serial Port Operation.......................................................... 35
I2C Serial Port Operation .......................................................... 38
Device Initialization and Calibration Flowcharts...................... 41
Power Dissipation and Thermal Considerations ...................... 46
Clock Speed and Driver Mode ................................................. 46
Evaluation of Operating Conditions ....................................... 46
Thermally Enhanced Package Mounting Guidelines ........... 47
Control Register Map .................................................................... 48
Control Register Map Bit Descriptions....................................... 52
Serial Control Port Configuration (Register 0x0000 to
Register 0x0001) ......................................................................... 52
Clock Part Family ID (Register 0x0003 to Register 0x0006) 53
SPI Version (Register 0x000B) ................................................. 53
Vendor ID (Register 0x000C to Register 0x000D)................ 53
IO_UPDATE (Register 0x000F) .............................................. 53
PLL1 Control (Register 0x0100 to Register 0x010B) ............ 54
PLL2 (Register 0x0200 to Register 0x0209)............................ 56
Clock Distribution (Register 0x300 to Register 0x0329) ...... 59
Power-Down Control (Register 0x0500 to Register 0x0504)63
Status Control (Register 0x0505 to Register 0x0509)............ 65
Outline Dimensions....................................................................... 67
Ordering Guide .......................................................................... 67
Rev. E | Page 2 of 67



Analog Devices AD9528
Data Sheet
REVISION HISTORY
2/2020—Rev. D to Rev. E
Changes to Endnote 1, Table 1........................................................4
Changes to Endnote 1, Table 21....................................................18
Changes to VCO Calibration Section ..........................................29
Changes to SYSREF Generator Section .......................................34
Change to Table 57 .........................................................................59
1/2018—Rev. C to Rev. D
Changes to Features Section and General Description
Section ................................................................................................. 1
Added Input Noise Sensitivity Parameter, Table 4 ......................6
Changes to HSTL Mode, Output Frequency Parameter, Test
Conditions/Comments Column, Table 8 and LVDS Mode,
3.5 mA, Output Frequency Parameter, Test
Conditions/Comments Column, Table 8 ......................................7
Changes to CS (Input) Parameter, Table 17 ...............................13
Changes to Figure 2 and Table 21.................................................16
Changes to Overview Section........................................................25
Added VCXO Input Section..........................................................27
Changes to PLL1 Reference Switchover Section ........................27
Changes to SPI/I2C Port Selection Section and Table 24 ..........35
Change to Figure 53........................................................................43
Changes to Table 49........................................................................56
Changes to Table 57........................................................................59
AD9528
7/2015—Rev. B to Rev. C
Changes to Differential Input Voltage, Sensitivity Frequency <
250 MHz Parameter and Differential Input Voltage, Sensitivity
Frequency > 250 MHz Parameter, Table 4 ..................................... 6
Changes to Figure 12 Caption, Figure 13 Caption, and Figure 14
Caption .............................................................................................20
Changes to Figure 15 Caption, Figure 16 Caption, Figure 17
Caption, and Figure 18 Caption ...................................................21
Changes to Figure 27 ......................................................................25
Changes to Implementation Specific Details Section ................35
Changes to I2C Serial Port Operation Section ............................38
4/2015—Rev. A to Rev. B
Changes to Serial Control Port Section and Table 24 ...............35
3/2015—Rev. 0 to Rev. A
Moved Revision History .................................................................. 3
Changes to Table 8............................................................................7
Changes to Voltage Parameter, Table 15.....................................12
Changes to Figure 2 ........................................................................16
Added Figure 13, Renumbered Sequentially ..............................20
Deleted Figure 17 ............................................................................21
Added Figure 15..............................................................................21
Changes to Figure 16 Caption.......................................................21
Changes to Figure 27 ......................................................................25
Changes to SYSREF Generator Section .......................................34
Changes to Serial Control Port Section and Implementation
Specific Details Section ..................................................................35
Changes to Table 36........................................................................48
Changes to Table 37........................................................................52
10/2014—Revision 0: Initial Version
Rev. E | Page 3 of 67







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)