Clock Translator. AD9554 Datasheet

AD9554 Translator. Datasheet pdf. Equivalent

AD9554 Datasheet
Recommendation AD9554 Datasheet
Part AD9554
Description Multiservice Line Card Adaptive Clock Translator
Feature AD9554; Data Sheet Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554 FEATURES .
Manufacture Analog Devices
Datasheet
Download AD9554 Datasheet




Analog Devices AD9554
Data Sheet
Quad PLL, Quad Input, Multiservice Line
Card Adaptive Clock Translator
AD9554
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no
disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and
ITU-T G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Quad digital phase-locked loop (DPLL) architecture with four
reference inputs (single-ended or differential)
4 × 4 crosspoint allows any reference input to drive any PLL
Input reference frequencies from 2 kHz to 1000 MHz
Reference validation and frequency monitoring: 2 ppm
Programmable input reference switchover priority
20-bit programmable input reference divider
8 differential clock outputs with each differential pair
configurable as HCSL, LVDS-compatible, or LVPECL-
compatible
Output frequency range: 430 kHz to 941 MHz
Programmable 18-bit integer and 24-bit fractional feedback
divider in digital PLL
Programmable loop bandwidths from 0.1 Hz to 4 kHz
Optional off-chip EEPROM to store power-up profile
72-lead (10 mm × 10 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and synchronous digital hierarchy (SDH) to optical
transport network (OTN) mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Cable infrastructure
Data communications
Professional video
GENERAL DESCRIPTION
The AD9554 is a low loop bandwidth clock translator that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9554 generates an output clock synchronized to up to four
external input references. The digital PLL (DPLL) allows for
reduction of input time jitter or phase noise associated with the
external references. The digitally controlled loop and holdover
circuitry of the AD9554 continuously generates a low jitter
output clock even when all reference inputs have failed.
The AD9554 operates over an industrial temperature range of
−40°C to +85°C. If a smaller device is needed, the AD9554-1 is
a version of this device with one output per PLL. If a single or
dual DPLL version of this device is needed, refer to the AD9557
or AD9559, respectively.
FUNCTIONAL BLOCK DIAGRAM
EXTERNAL
EEPROM
(OPTIONAL)
STABLE
SOURCE
STATUS AND
CONTROL PINS
REFERENCE
INPUT
MONITOR
AND MUX
CLOCK
MULTIPLIER
SERIAL INTERFACE
(SPI OR I2C)
DIGITAL
PLL 0
DIGITAL
PLL 1
ANALOG
PLL 0
ANALOG
PLL 1
P0 DIVIDER
P1 DIVIDER
DIGITAL
PLL 2
ANALOG
PLL 2
P2 DIVIDER
DIGITAL
PLL 3
ANALOG
PLL 3
P3 DIVIDER
AD9554
Figure 1.
Q0_A DIVIDER
Q0_B DIVIDER
Q1_A DIVIDER
Q1_B DIVIDER
Q2_A DIVIDER
Q2_B DIVIDER
Q3_A DIVIDER
Q3_B DIVIDER
Rev. D
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Analog Devices AD9554
AD9554
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital PLL (DPLL) Core .......................................................... 35
Applications....................................................................................... 1
Loop Control State Machine..................................................... 38
General Description ......................................................................... 1
System Clock (SYSCLK) ................................................................ 39
Functional Block Diagram .............................................................. 1
SYSCLK Inputs ........................................................................... 39
Revision History ............................................................................... 4
SYSCLK Multiplier..................................................................... 39
Specifications..................................................................................... 5
Output Analog PLL (APLL).......................................................... 41
Supply Voltage............................................................................... 5
APLL Configuration .................................................................. 41
Supply Current.............................................................................. 5
APLL Calibration ....................................................................... 41
Power Dissipation......................................................................... 6
Clock Distribution.......................................................................... 42
System Clock Inputs (XOA, XOB) ............................................. 6
Clock Dividers ............................................................................ 42
Reference Inputs ........................................................................... 7
Output Amplitude and Power-Down ...................................... 42
Reference Monitors ...................................................................... 8
Clock Distribution Synchronization........................................ 43
Reference Switchover Specifications.......................................... 8
Status and Control.......................................................................... 44
Distribution Clock Outputs ........................................................ 9
Multifunction Pins (M0 to M9) ............................................... 44
Time Duration of Digital Functions ........................................ 11
IRQ Function .............................................................................. 44
Digital PLL (DPLL_0, DPLL_1, DPLL_2, and DPLL_3) ...... 11
Watchdog Timer......................................................................... 45
Analog PLL (APLL_0, APLL_1, APLL_2, and APLL_3) ...... 11
EEPROM ..................................................................................... 45
Digital PLL Lock Detection ...................................................... 12
Serial Control Port ......................................................................... 49
Holdover Specifications ............................................................. 12
SPI/I2C Port Selection................................................................ 49
Serial Port Specifications—Serial Port Interface (SPI) Mode12
Serial Port Specifications—I2C Mode ...................................... 13
SPI Serial Port Operation .......................................................... 49
I2C Serial Port Operation .......................................................... 52
Logic Inputs (RESET, M9 to M0)............................................. 14
Logic Outputs (M9 to M0) ........................................................ 14
Jitter Generation ......................................................................... 15
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 21
Input/Output Termination Recommendations .......................... 24
Getting Started ................................................................................ 25
Chip Power Monitor and Startup............................................. 25
Multifunction Pins at Reset/Power-Up ................................... 25
Device Register Programming Using a Register Setup File .. 25
Register Programming Overview............................................. 30
Theory of Operation ...................................................................... 33
Overview...................................................................................... 33
Reference Input Physical Connections .................................... 34
Reference Monitors .................................................................... 34
Reference Input Block................................................................ 34
Programming the Input/Output Registers.................................. 55
Buffered/Active Registers.......................................................... 55
Write Detect Registers ............................................................... 55
Autoclear Registers..................................................................... 55
Register Access Restrictions...................................................... 55
Thermal Performance .................................................................... 56
Power Supply Partitions................................................................. 57
VDD Supplies ............................................................................. 57
VDD_SP Supply ......................................................................... 57
Register Map ................................................................................... 58
Register Map Bit Descriptions ...................................................... 70
Serial Control Port Configuration (Register 0x0000 to
Register 0x0001) ......................................................................... 70
Clock Part Family ID (Register 0x0003 to Register 0x0006) 71
SPI Version (Register 0x000B).................................................. 71
Vendor ID (Register 0x000C to Register 0x000D) ................ 71
IO_Update (Register 0x000F)................................................... 71
User Scratchpad (Register 0x00FE to Register 0x00FF) ....... 71
Reference Switchover ................................................................. 35
Rev. D | Page 2 of 116



Analog Devices AD9554
Data Sheet
AD9554
General Configuration (Register 0x0100 to Register 0x010E)
....................................................................................................... 72
IRQ Mask (Register 0x010F to Register 0x011F)....................73
System Clock (Register 0x0200 to Register 0x0208) ..............75
Reference Input A (Register 0x0300 to Register 0x031E)......76
Reference Input B (Register 0x0320 to Register 0x033E) ......78
Reference Input C (Register 0x0340 to Register 0x035E)......78
Reference Input D (Register 0x0360 to Register 0x037E) .....78
DPLL_0 Controls (Register 0x0400 to Register 0x041E).......78
APLL_0 Configuration (Register 0x0430 to Register 0x0434)
....................................................................................................... 80
Output PLL_0 (APLL_0) Sync and Clock Distribution
(Register 0x0434 to Register 0x043E).......................................81
DPLL_0 Settings for Reference Input A (REFA) (Register
0x0440 to Register 0x044C).......................................................83
DPLL_0 Settings for Reference Input B (REFB) (Register
0x044D to Register 0x0459).......................................................84
DPLL_0 Settings for Reference Input C (REFC) (Register
0x045A to Register 0x0466).......................................................85
DPLL_0 Settings for Reference Input D (REFD) (Register
0x0467 to Register 0x0473)........................................................86
DPLL_1 Controls (Register 0x0500 to Register 0x051E).......87
APLL_1 Configuration (Register 0x0530 to Register 0x0533)
....................................................................................................... 87
PLL_1 Output Sync and Clock Distribution (Register 0x0534
to Register 0x053E) .....................................................................87
DPLL_1 Settings for Reference Input A (REFA) (Register
0x0540 to Register 0x054C).......................................................87
DPLL_1 Settings for Reference Input B (REFB) (Register
0x054D to Register 0x0559).......................................................87
DPLL_1 Settings for Reference Input C (REFC) (Register
0x055A to Register 0x0566).......................................................87
DPLL_1 Settings for Reference Input D (REFD) (Register
0x0567 to Register 0x0573)........................................................87
DPLL_2 Controls (Register 0x0600 to Register 0x061E).......87
APLL_2 Configuration (Register 0x0630 to Register 0x0633)
....................................................................................................... 87
PLL_2 Output Sync and Clock Distribution (Register 0x0634
to Register 0x063E) .....................................................................88
DPLL_2 Settings for Reference Input A (REFA) (Register
0x0640 to Register 0x064C).......................................................88
DPLL_2 Settings for Reference Input B (REFB) (Register
0x064D to Register 0x0659).......................................................88
DPLL_2 Settings for Reference Input C (REFC) (Register
0x065A to Register 0x0666).......................................................88
DPLL_2 Settings for Reference Input D (REFD) (Register
0x0667 to Register 0x0673)........................................................88
DPLL_3 Controls (Register 0x0700 to Register 0x071E) ......88
APLL_3 Configuration (Register 0x0730 to Register 0x0733)
....................................................................................................... 88
PLL_3 Output Sync and Clock Distribution (Register 0x0734
to Register 0x073E).....................................................................88
DPLL_3 Settings for Reference Input A (REFA) (Register
0x0740 to Register 0x074C).......................................................88
DPLL_3 Settings for Reference Input B (REFB) (Register
0x074D to Register 0x0759) ......................................................88
DPLL_3 Settings for Reference Input C (REFC) (Register
0x075A to Register 0x0766).......................................................88
DPLL_3 Settings for Reference Input D (REFD) (Register
0x0767 to Register 0x0773)........................................................88
Digital Loop Filter Coefficients (Register 0x0800 to Register
0x0817) .........................................................................................89
Common Operational Controls (Register 0x0A00 to Register
0x0A0E) ........................................................................................ 90
IRQ Clearing (Register 0x0A05 to Register 0x0A14) ............92
PLL_0 Operational Controls (Register 0x0A20 to Register
0x0A24) ........................................................................................95
PLL_1 Operational Controls (Register 0x0A40 to Register
0x0A44) ........................................................................................97
PLL_2 Operational Controls (Register 0x0A60 to Register
0x0A64) ........................................................................................97
PLL_3 Operational Controls (Register 0x0A80 to Register
0x0A84) ........................................................................................97
Voltage Regulator (Register 0x0B00 to Register 0x0B01)......97
Status ReadBack (Register 0x0D00 to Register 0x0D05).......97
IRQ Monitor (Register 0x0D08 to Register 0x0D16) ............99
PLL_0 Read Only Status (Register 0x0D20 to Register
0x0D2A) .....................................................................................102
PLL_1 Read Only Status (Register 0x0D40 to Register
0x0D4A) .....................................................................................104
PLL_2 Read Only Status (Register 0x0D60 to Register
0x0D6A) .....................................................................................104
PLL_3 Read Only Status (Register 0x0D80 to Register
0x0D8A) .....................................................................................104
EEPROM Control (Register 0x0E00 to Register 0x0E03) ...104
EEPROM Storage Sequence (Register 0x0E10 to Register
0x0E61) ....................................................................................... 105
Outline Dimensions......................................................................116
Ordering Guide .........................................................................116
Rev. D | Page 3 of 116







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