Frequency Synthesizer. ADF4153A Datasheet

ADF4153A Synthesizer. Datasheet pdf. Equivalent

ADF4153A Datasheet
Recommendation ADF4153A Datasheet
Part ADF4153A
Description Fractional-N Frequency Synthesizer
Feature ADF4153A; Data Sheet Fractional-N Frequency Synthesizer ADF4153A FEATURES GENERAL DESCRIPTION RF bandwidth.
Manufacture Analog Devices
Datasheet
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Analog Devices ADF4153A
Data Sheet
Fractional-N Frequency Synthesizer
ADF4153A
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP SDVDD
RSET
ADF4153A
REFIN
MUXOUT
×2
DOUBLER
4-BIT
R COUNTER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
THIRD ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CURRENT
SETTING
CP
RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. A
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ADF4153A* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
ADF4153A Evaluation Board
DOCUMENTATION
Data Sheet
ADF4153A: Fractional-N Frequency Synthesizer Data
Sheet
User Guides
UG-485: Evaluation Board for the ADF4153A Fractional-N
PLL Frequency Synthesizer
REFERENCE MATERIALS
Press
• Analog Devices’ 4-GHz PLL Synthesizer Offers Leading
Phase Noise Performance
Product Selection Guide
RF Source Booklet
DESIGN RESOURCES
ADF4153A Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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Analog Devices ADF4153A
ADF4153A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 8
Reference Input Section............................................................... 8
RF Input Stage............................................................................... 8
RF INT Divider............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
RF R Counter ................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect........................................................ 9
Input Shift Registers ..................................................................... 9
Program Modes ............................................................................ 9
Register Maps .................................................................................. 10
REVISION HISTORY
1/13—Rev. 0 to Rev. A
Added TSSOP Package ...................................................... Universal
Added Figure 3, Renumbered Sequentially ...................................6
Updated Outline Dimensions ........................................................22
Changes to Ordering Guide ...........................................................22
10/12—Revision 0: Initial Version
Data Sheet
N Divider Register, R0 ............................................................... 15
R Divider Register, R1................................................................ 15
Control Register, R2 ................................................................... 15
Noise and Spur Register, R3...................................................... 16
Reserved Bits............................................................................... 16
Initialization Sequence .............................................................. 17
RF Synthesizer: A Worked Example ........................................ 17
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus ................................................ 17
Fastlock with Spurious Optimization...................................... 18
Spur Mechanisms ....................................................................... 18
Spur Consistency........................................................................ 19
Phase Resync............................................................................... 19
Filter Design—ADIsimPLL....................................................... 19
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip Scale Package .................... 20
Applications Information .............................................................. 21
Local Oscillator for a GSM Base Station Transmitter ........... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
Rev. A | Page 2 of 24







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