Integrated DCL. ADATE320 Datasheet

ADATE320 DCL. Datasheet pdf. Equivalent

ADATE320 Datasheet
Recommendation ADATE320 Datasheet
Part ADATE320
Description 1.25 GHz Dual Integrated DCL
Feature ADATE320; Data Sheet 1.25 GHz Dual Integrated DCL with PPMU, Level Setting DACs, and On-Chip Calibration Regi.
Manufacture Analog Devices
Datasheet
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Analog Devices ADATE320
Data Sheet
1.25 GHz Dual Integrated DCL with PPMU, Level
Setting DACs, and On-Chip Calibration Registers
ADATE320
FEATURES
1.25 GHz, 2.5 Gbps data rate
3-level driver with high-Z and reflection clamps
Window and differential comparators
±25 mA active load
Per pin parametric measurement unit (PMU) with a −1.5 V to
+4.5 V range
Low leakage mode (typically <5 nA)
Integrated 16-bit DACs with offset and gain correction
1.2 W power dissipation per channel (ADATE320)
1.3 W power dissipation per channel (ADATE320-1)
Driver
Voltage range: −1.5 V to +4.5 V
Precision trimmed termination: 50.0 Ω
Unterminated swing: 50 mV minimum to 6.0 V maximum
400 ps minimum pulse width, 1.0 V programmed swing
25 ps deterministic jitter
Comparator
Differential and single-ended window modes
100 ps equivalent input rise/fall time (ERT/EFT)
250 mV current mode logic (CML) outputs (ADATE320)
400 mV CML outputs (ADATE320-1)
Load
Per pin PMU (PPMU)
Force voltage/compliance range: −1.5 V to +4.5 V
5 current ranges
±40 mA, ±1 mA, ±100 μA, ±10 µA, ±2 µA
Dedicated go/no-go comparators
DC levels
Fully integrated and dedicated 16-bit DACs
On-chip gain and offset calibration registers with
automatic add/multiply function
84-lead, 10 mm × 10 mm LFCSP (0.4 mm pitch)
APPLICATIONS
Automatic test equipment (ATE)
Semiconductor/board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE320 is a complete, single-chip ATE solution that
performs the pin electronics functions of a driver, comparator,
and active load (DCL), and a four quadrant per pin parametric
measurement unit (PPMU). Dedicated 16-bit digital-to-analog
converters (DACs) with on-chip calibration registers provide all
the necessary dc levels for operation of the device.
The driver features three active modes: high, low, and terminate, as
well as a high impedance inhibit state. The inhibit state, in
conjunction with the integrated dynamic clamps, facilitates
significant attenuation of transmission line reflections when the
driver is not actively terminating the line. The open-circuit drive
capability is −1.5 V to +4.5 V to accommodate a standard range
of ATE and instrumentation applications.
The ADATE320 can be used as a dual, single-ended pin
electronics channel or as a single differential channel. In
addition to per channel high speed window comparators, the
ADATE320 provides a programmable threshold differential
comparator for differential ATE applications.
All dc levels for DCL and PPMU functions are generated by
dedicated, on-chip, 16-bit DACs. To facilitate the programming
of accurate levels, the ADATE320 includes an integrated
calibration function to correct for the gain and offset errors of
each functional block. Correction coefficients can be stored on
chip, and any values written to the DACs adjust automatically
using the appropriate correction factors.
The ADATE320 uses a serial programmable interface (SPI) bus
to program all functional blocks, DACs, and on-chip calibration
constants. It also has an on-chip temperature sensor and overvolt-
age/undervoltage fault clamps that monitor and report the
device temperature and any output pin or transient PPMU
voltage faults that may occur during operation.
The ADATE320 is available in two options. The standard option
has high speed comparator outputs with 250 mV output swing.
The ADATE320-1 has 400 mV output swing. See the Ordering
Guide for more information.
Rev. B
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DOCUMENTATION
Data Sheet
ADATE320: 1.25 GHz Dual Integrated DCL with PPMU,
Level Setting DACs, and On-Chip Calibration Registers
Data Sheet
DESIGN RESOURCES
ADATE320 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
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Analog Devices ADATE320
ADATE320
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Electrical Specifications ............................................................... 4
Driver Specifications .................................................................... 5
Reflection Clamp Specifications................................................. 7
Normal Window Comparator (NWC) Specifications............. 8
Differential Mode Comparator (DMC) Specifications ......... 10
Active Load Specifications ........................................................ 11
PPMU Specifications ................................................................. 13
PPMU Go/No-Go Comparators Specifications..................... 18
PPMU External Sense Pins Specifications .............................. 18
VREF, VREFGND, and DUTGND Reference Input Pins
Specifications .............................................................................. 19
Temperature Monitor Specifications ....................................... 19
Alarm Functions Specifications................................................ 19
Serial Programmable Interface (SPI) Specifications.............. 20
SPI Timing Specifications ......................................................... 20
SPI Timing Diagrams................................................................. 21
Absolute Maximum Ratings.......................................................... 25
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changes to Time Constant 1 Parameter and Time Constant 2
Parameter, Table 2............................................................................. 7
Changes to IOx Offset Parameter, and IOHx Offset
Parameter, Table 6........................................................................... 11
Change to AGND Pin Number Column..................................... 29
Change to SPI Reset Sequence and the RST Pin Section .......... 50
Changes to the SPI Clock Cycles and BUSY Pin Section.......... 51
Changes to Table 24........................................................................ 54
Changes to Figure 137.................................................................... 65
10/2015—Revision A: Initial Version
Data Sheet
Thermal Characteristics ............................................................ 25
Explanation of Test Levels......................................................... 25
ESD Caution................................................................................ 25
User Information and Truth Tables ......................................... 26
Pin Configuration and Function Descriptions........................... 28
Typical Performance Characteristics ........................................... 30
Theory of Operation ...................................................................... 50
Serial Programmable Interface (SPI)....................................... 50
Level Setting DACs .................................................................... 52
Alarm Functions......................................................................... 59
Applications Information .............................................................. 62
Power Supply, Grounding, and Typical Decoupling Strategy
....................................................................................................... 62
Power Supply Sequencing ......................................................... 64
Detailed Functional Block Diagrams........................................... 65
SPI Register Memory Map and Details ....................................... 71
Memory Map .............................................................................. 71
Register Details ........................................................................... 74
Default Test Conditions................................................................. 80
External Components .................................................................... 81
Outline Dimensions ....................................................................... 82
Ordering Guide .......................................................................... 82
Rev. B | Page 2 of 82







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