Clock Generator. CY2292 Datasheet

CY2292 Generator. Datasheet pdf. Equivalent

CY2292 Datasheet
Recommendation CY2292 Datasheet
Part CY2292
Description Three-PLL General-Purpose EPROM-Programmable Clock Generator
Feature CY2292; CY2292 Three-PLL General-Purpose EPROM-Programmable Clock Generator Three-PLL General-Purpose EPROM.
Manufacture Cypress Semiconductor
Datasheet
Download CY2292 Datasheet




Cypress Semiconductor CY2292
CY2292
Three-PLL General-Purpose
EPROM-Programmable Clock Generator
Three-PLL General-Purpose EPROM-Programmable Clock Generator
Features
Benefits
Three integrated phase locked loops (PLLs)
Erasable programmable read only memory (EPROM)
programmability
Factory programmable (CY2292) or field programmable
(CY2292F) device options
Low-skew, low-jitter, high accuracy outputs
Power management options (shutdown, OE, suspend)
Frequency select option
Smooth slewing on CPUCLK
Configurable 3.3 V or 5 V operation
16-pin small-outline integrated circuit (SOIC) package
(CY2292F also in TSSOP)
Generates up to three custom frequencies from one external
source
Easy customization and fast turnaround
Programming support available for all opportunities
Supports low power applications
Eight user selectable frequencies on CPU PLL
Allows downstream PLLs to stay locked on CPUCLK output
Industry standard packaging saves on board space
Functional Description
For a complete list of related documentation, click here.
Selector Guide
Part Number
Input Frequency Range
Output Frequency Range
Specifics
CY2292SC, SL, SXC, SXL 10 MHz to 25 MHz (external crystal) 76.923 kHz to 100 MHz (5 V) Factory programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 80 MHz (3.3 V) Commercial temperature
CY2292SI, SXI
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Factory programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Industrial temperature
CY2292F, FXC, FZX
10 MHz to 25 MHz (external crystal) 76.923 kHz to 90 MHz (5 V) Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 66.6 MHz (3.3 V) Commercial temperature
CY2292FXI, FZXI
10 MHz to 25 MHz (external crystal) 76.923 kHz to 80 MHz (5 V) Field programmable
1 MHz to 30 MHz (reference clock) 76.923 kHz to 60.0 MHz (3.3 V) Industrial temperature
Logic Block Diagram
XTALIN
XTALOUT
S0
S1
S2 / SUSPEND
OSC.
CPLL
( 8 BIT)
UPLL
( 10 BIT)
SPLL
( 8 BIT)
/1,2,4
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96, 104
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
SHUTDOWN / OE
CONFIG
EPROM
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07449 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 26, 2016



Cypress Semiconductor CY2292
CY2292
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Operation ........................................................................... 4
Output Configuration ................................................... 4
Power Saving Features ............................................... 4
CyClocks Software ........................................................... 4
Cypress FTG Programmer ............................................... 4
Custom Configuration Request Procedure .................... 4
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 6
Electrical Characteristics ................................................. 6
Electrical Characteristics ................................................. 7
Electrical Characteristics ................................................. 7
Test Circuit ........................................................................ 8
Switching Characteristics ................................................ 9
Switching Characteristics .............................................. 10
Switching Characteristics .............................................. 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 14
Possible Configurations ............................................. 14
Ordering Code Definitions ......................................... 14
Package Characteristics ................................................ 15
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-07449 Rev. *L
Page 2 of 19



Cypress Semiconductor CY2292
CY2292
Pinouts
Figure 1. 16-pin SOIC / TSSOP pinout
CLKC
VDD
GND
XTALIN
XTALOUT
XBUF
CLKD
CPUCLK
1
2
3
4
5
6
7
8
16 SHUTDOWN/OE
15 S2/SUSPEND
14 VDD
13 S1
12 S0
11 GND
10 CLKA
9 CLKB
Pin Definitions
Name
CLKC
VDD
GND
XTALIN[1]
XTALOUT[1, 2]
XBUF
CLKD
CPUCLK
CLKB
CLKA
S0
S1
S2/SUSPEND
SHUTDOWN/OE
Pin Number
Description
1 Configurable clock output C.
2, 14 Voltage supply.
3, 11 Ground.
4 Reference crystal input or external reference clock input.
5 Reference crystal feedback.
6 Buffered reference clock output.
7 Configurable clock output D.
8 CPU frequency clock output.
9 Configurable clock output B.
10 Configurable clock output A.
12 CPU clock select input, bit 0.
13 CPU clock select input, bit 1.
15 CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
16 Places outputs in tristate[3] condition and shuts down chip when LOW. Optionally, only places
outputs in tristate[3] condition and does not shut down chip when LOW.
Notes
1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
Document Number: 38-07449 Rev. *L
Page 3 of 19







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