Clock Generator. CY27410 Datasheet

CY27410 Generator. Datasheet pdf. Equivalent

CY27410 Datasheet
Recommendation CY27410 Datasheet
Part CY27410
Description 4-PLL Spread-Spectrum Clock Generator
Feature CY27410; CY27410 4-PLL Spread-Spectrum Clock Generator 4-PLL Spread-Spectrum Clock Generator Features ■ Inpu.
Manufacture Cypress Semiconductor
Datasheet
Download CY27410 Datasheet




Cypress Semiconductor CY27410
CY27410
4-PLL Spread-Spectrum Clock Generator
4-PLL Spread-Spectrum Clock Generator
Features
Input frequencies
Crystal input: 8 MHz to 48 MHz
Reference clock: 8 MHz to 250 MHz LVCMOS
Reference clock: 8 MHz to 700 MHz differential
Output frequencies
25 MHz to 700 MHz LVDS, LVPECL, HCSL, CML
3 MHz to 250 MHz LVCMOS
1 kHz to 8 MHz for one LVCMOS output
RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset
PCIe 1.0/2.0/3.0 compliant
SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant
Logic Block Diagram
Maximum 12 outputs split in two banks with six outputs each.
Up to eight differential output pairs (HCSL, LVPECL, CML,
or LVDS)
Up to 12 LVCMOS outputs
Up to 100-ps skew for differential outputs within a bank
Four fractional N-type phase-locked loops (PLLs) with
VCXO (±120 ppm with steps of 0.23 ppm)
Spread-spectrum capability (Logic SS and Lexmark profile
0.1% to 5% in 0.1% steps, down or center spread)
Supply voltage: 1.8 V, 2.5 V, and 3.3 V
Zero-delay buffer (ZDB) and non-zero delay buffer (NZDB)
configurations
I2C configurable with onboard programming
Industrial-grade device, offered in 48-pin QFN (7 × 7 × 1.0 mm)
package
XIN
XOUT
IN1P
IN1N
IN2P
IN2N
Reference
System
INI
IN1S
IN2S
INC
Output Drivers 1
O1[1..4]
PLL1
O2[1..4]
PLL2
PLL3
O3[1..4]
PLL4
O4[1..4]
Output Drivers 2
Register
Memory
NV
Memory
PRG
Block
ADC
FS
I2C
RCAL
VIN
FS2
FS1
FS0
SCLK
SDAT
RCCAL
BG
OSC
POR
QP
LDOs
VDD
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-89074 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 14, 2016



Cypress Semiconductor CY27410
CY27410
Contents
Functional Description ..................................................... 3
Input System ............................................................... 3
VCXO Input Block ....................................................... 3
Frequency Select Input ............................................... 3
I2C Block (SCLK, SDAT) ............................................. 4
Synthesis Section ........................................................ 4
Output Section ............................................................. 4
Onboard Programming ................................................ 5
Functional Features
and Application Considerations .......................................... 5
Pinouts ............................................................................ 10
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 13
Operating Temperature ............................................. 13
Operating Power Supply ........................................... 13
DC Chip-Level Specifications .................................... 14
DC Output Specifications .......................................... 15
AC Input Clock Specifications ................................... 16
AC Output Specifications .......................................... 16
Test and Measurement Circuits ................................ 22
Voltage and Timing Definitions .................................. 23
Packaging Information ................................................... 25
Solder Reflow Specifications ..................................... 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 001-89074 Rev. *K
Page 2 of 29



Cypress Semiconductor CY27410
CY27410
Functional Description
The CY27410 is a standard-performance programmable clock
generator with four independent fractional PLLs, which
generates any frequency with a zero-ppm synthesis error. Each
PLL is followed by a set of four independent dividers to generate
four different frequencies from a single PLL. All four dividers are
synchronized to generate phase-aligned clock outputs with
minimal skew. The PLLs also support the spread-spectrum
feature to reduce EMI. PLL 1 has VCXO functionality to achieve
ppm granularity of output frequency.
The CY27410 accepts a crystal clock or a
single-ended/differential reference clock. The device supports
up to 12 outputs, divided into two banks with six outputs each.
Four outputs of PLL 1 and PLL 2 are multiplexed to
output Bank 1, and four clock outputs of PLL 3 and PLL 4 are
multiplexed to output Bank 2. The 12 outputs of the two banks
are configurable as eight differential outputs, 12 single-ended
outputs, or a combination of differential and single-ended
outputs.
The CY27410 has an on-chip volatile and nonvolatile memory,
composed of eight registers, which store the device
configuration settings. These registers can be accessed and
programmed onboard through the I2C interface. You can also
configure the device on-the-fly to completely reprogram the
device on the application board. Besides the I2C interface,
external signals can be applied to multifunction pins for different
functions such as the following:
Dynamically change the output frequency
Output enable/disable
Power down
Spread ON/OFF
One low-frequency clock output, in kilohertz, is provided to meet
the need of widely used reference frequencies, such as
32.768 kHz. The jitter specs of the CY27410 make it an ideal
choice for the following communication protocols: PCIe
1.0/2.0/3.0, USB 2.0/3.0, SATA 1.0/2.0, and 1/10GbE.
Input System
The input system supports the following (see Figure 1):
XIN/XOUT supports crystal input.
IN1 supports differential and single-ended clock inputs.
IN2 supports differential and single-ended clock inputs.
Figure 1. Oscillator/Clock Input Block Diagram
XIN
XOUT XO
INC
MUX
INI
IN1P
IN1N
DIV-R1
IN1S
If a crystal is used, XIN and XOUT are connected to a crystal
oscillator to generate the required internal frequency, as shown
in Figure 2. The supported differential tuning capacitor range is
8 pF to 12 pF.
Figure 2. Connecting a Crystal
Crystal
XIN
XO
XOUT
IN1 and IN2 are designed to accept either a single-ended or
differential reference input. IN2 can be used to accept the
feedback signal to implement the ZDB functionality of the device.
The differential inputs are capable of interfacing with multiple
standards, such as LVPECL, LVDS, CML, and HCSL. The
differential signals must be of AC-coupling, as shown in Figure 3.
Figure 3. Interfacing Differential and Single-Ended Signals
Differential Signal
100 pF
Termination
100 pF
RS
LVCMOS Signal
INxP
INxN
INxP
INxN
VCXO Input Block
The VIN input is used for the VCXO functionality of the device.
In this functionality, the output can change with respect to an
input voltage required for audio-visual applications. The output
frequency can vary up to ±120 ppm. This input voltage directly
controls the PLL 1 fractional divider to provide the VCXO
functionality.
Frequency Select Input
The CY27410 supports frequency-select features with which the
customer can change output frequencies on-the-fly. The device
has eight configuration register sets, which can be
preprogrammed or written through I2C. Changing the signal level
of the FS pins (high and low) selects the appropriate
configuration registers and changes the output frequency
accordingly.
IN2P
IN2N
DIV-R2
IN2S
Document Number: 001-89074 Rev. *K
Page 3 of 29







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