GaAs MMIC. NJG1635AHB6 Datasheet

NJG1635AHB6 MMIC. Datasheet pdf. Equivalent

NJG1635AHB6 Datasheet
Recommendation NJG1635AHB6 Datasheet
Part NJG1635AHB6
Description SPDT SWITCH GaAs MMIC
Feature NJG1635AHB6; NJG1635AHB6 SPDT SWITCH GaAs MMIC I GENERAL DESCRIPTION NJG1635AHB6 is a GaAs SPDT switch IC suite.
Manufacture New Japan Radio
Datasheet
Download NJG1635AHB6 Datasheet




New Japan Radio NJG1635AHB6
NJG1635AHB6
SPDT SWITCH GaAs MMIC
I GENERAL DESCRIPTION
NJG1635AHB6 is a GaAs SPDT switch IC suited for mobile
handset, WiBro and WiMAX devices. This switch features high power
handling, low insertion loss, high isolation.
This switch includes logic decoder function, and can be operated by
single bit control signal from 1.3V of logical high voltage. In addition,
this switch includes ESD protection circuits.
The ultra-small & ultra-thin USB8-B6 package is adopted.
I PACKAGE OUTLINE
NJG1635AHB6
I APPLICATIONS
LTE, UMTS, CDMA and WiMAX applications
Mobile phone, Data card, Tablet PC and Femtocell applications
Antenna switching, Bands switching and Post PA switching applications
General Purpose Switching application
I FEATURES
G Single bit low voltage control
G Operation supply voltage
G Low insertion loss
G High isolation
G High power handling
G ESD protection circuit
G Small & thin package
+1.3V~+4.5V
+2.5~+4.5V
0.30dB typ. @f=0.9GHz, PIN=30dBm, VDD=2.7V
0.35dB typ. @f=1.9GHz, PIN=30dBm, VDD=2.7V
0.40dB typ. @f=2.7GHz, PIN=30dBm, VDD=2.7V
35dB typ. @f=0.9/1.9GHz, PIN=30dBm, VDD=2.7V
33dB typ. @f=2.7GHz, PIN=30dBm, VDD=2.7V
P-0.1dB=32dBm min. @f=2.7GHz, VDD=2.7V
USB8-B6 (Package size: 1.5 x 1.5 x 0.55mm)
I PIN CONFIGURATION
(Top view)
4
5
3
62
I TRUTH TABLE
71
8
Pin connection
1. P1
2. GND
3. P2
4. GND
5. VCTL
6. PC
7. VDD
8. GND
Control Voltage: “H”=VCTL (H), “L”=VCTL (L)
VCTL
PATH
H P1-PC
L P2-PC
NOTE: Please note that any information on this datasheet will be subject to change
Ver.2013-05-09
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New Japan Radio NJG1635AHB6
NJG1635AHB6
I ABSOLUTE MAXIMUM RATINGS
PARAMETER
RF Input Power
Supply Voltage
Control Voltage
Power Dissipation
Operating Temp.
Storage Temp.
SYMBOL
CONDITIONS
PIN VDD=2.7V, VCTL=0/1.8V
VDD VDD terminal
VCTL
PD
Topr
Tstg
VCTL terminal
on PCB board
(Ta=+25°C, Zs=Zl=50))
CONDITIONS UNITS
35 dBm
5.0 V
5.0 V
160 mW
-40~+95
°C
-55~+150
°C
I ELECTRICAL CHARACTERISTICS
(General conditions: VDD=2.7V, VCTL(L)=0V, VCTL(H)=1.8V, ZS=Zl=50, Ta=+25°C, with application circuit)
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Voltage
Operating Current
Control Voltage (LOW)
Control Voltage (HIGH)
Control Current
Insertion Loss 1
Insertion Loss 2
Insertion Loss 3
Isolation 1
VDD
IDD
VCTL(L)
VCTL(H)
ICTL
LOSS1
LOSS2
LOSS3
ISL1
PIN=30dBm
f=0.9GHz, PIN=30dBm
f=1.9GHz, PIN=30dBm
f=2.7GHz, PIN=30dBm
f=0.9GHz, PIN=30dBm
2.5 2.7 4.5
V
- 25 50 µA
0 - 0.4 V
1.3 1.8 4.5
V
- 5 10 µA
- 0.30 0.45 dB
- 0.35 0.50 dB
- 0.40 0.60 dB
32 35 - dB
Isolation 2
Isolation 3
Input Power at
0.1dB Compression
2nd Harmonics 1
ISL2
ISL3
P-0.1dB
2fo(1)
f=1.9GHz, PIN=30dBm
f=2.7GHz, PIN=30dBm
f=2.7GHz
f=0.9GHz, PIN=26dBm
30 35 - dB
25 33 - dB
32 -
- dBm
- -75 -65 dBc
2nd Harmonics 2
2fo(2) f=1.9GHz, PIN=26dBm
- -75 -65 dBc
3rd Harmonics 1
3fo(1) f=0.9GHz, PIN=26dBm
- -80 -65 dBc
3rd Harmonics 2
Input 3rd Order
Intercept Point 1
Input 3rd Order
Intercept Point 2
VSWR (PC, P1, P2)
3fo(2)
IIP3(1)
IIP3(2)
VSWR
f=1.9GHz, PIN=26dBm
f=0.9GHz+0.901GHz
PIN=25dBm each
f=1.9GHz+1.901GHz
PIN=25dBm each
f=2.7GHz, ON State
- -80 -65 dBc
58 64
- dBm
58 62
- dBm
- 1.2 1.4
Switching time
TSW
PC-P1, PC-P2 port
switching time
- 2 5 µs
The input 3rd order intercept point is defined as following equation, IIP3 = (3 x Pout – IM3)/2 + LOSS
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New Japan Radio NJG1635AHB6
NJG1635AHB6
I TERMINAL INFORMATION
No. SYMBOL
DESCRIPTION
This port is connected to PC port by control voltage of +1.3~4.5V(VCTL(H))
1 P1 to 5th pin. An external capacitor is required to block the DC bias voltage
of internal circuit.
2
GND
Ground terminal. Please connect this terminal with ground plane as
close as possible for excellent RF performance.
This port is connected to PC port by control voltage of +0.0~0.4V(VCTL(L))
3 P2 to 5th pin. An external capacitor is required to block the DC bias voltage
of internal circuit.
4
GND
Ground terminal. Please connect this terminal with ground plane as
close as possible for excellent RF performance.
Control port. This terminal is set to +1.3V~4.5V of logical high level for
5 VCTL ON state between PC and P1 RF ports, and set to +0.0~0.4V of logical
low level for ON state between PC and P2 RF ports.
Common RF port. This PC port is connected to P1 or P2 by logical
6
PC
control voltage of VCTL.
In order to block DC bias voltage of internal circuit, an external capacitor
is required.
7
VDD
A supply voltage terminal (+2.5~+4.5V). Please place a bypass
capacitor between this and GND for avoiding RF noise from outside.
8
GND
Ground terminal. Please connect this terminal with ground plane as
close as possible for excellent RF performance.
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