HDMI/DVI Buffer. AD8195 Datasheet

AD8195 Buffer. Datasheet pdf. Equivalent

AD8195 Datasheet
Recommendation AD8195 Datasheet
Part AD8195
Description HDMI/DVI Buffer
Feature AD8195; Data Sheet HDMI/DVI Buffer with Equalization AD8195 FEATURES 1 input, 1 output HDMI/DVI link Enabl.
Manufacture Analog Devices
Datasheet
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Analog Devices AD8195
Data Sheet
HDMI/DVI Buffer with Equalization
AD8195
FEATURES
1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 m at 2.25 Gbps)
Preemphasized outputs
Fully buffered unidirectional inputs/outputs
50 Ω on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input termination
3 auxiliary buffered channels per link
Bidirectional buffered DDC lines (SDA and SCL)
Bidirectional buffered CEC line with integrated pull-up
resistors (27 kΩ)
Independently powered from 5 V of HDMI input
connector
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation
Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm × 6 mm)
APPLICATIONS
Front panel buffer for advanced television (HDTV) sets
GENERAL DESCRIPTION
The AD8195 is an HDMI/DVI buffer featuring equalized TMDS
inputs and preemphasized TMDS outputs, ideal for systems with
long cable runs. The AD8195 includes bidirectional buffering
for the DDC bus and bidirectional buffering with integrated
pull-up resistors for the CEC bus. The DDC and CEC buffers
are powered independently of the TMDS buffers so that DDC/
CEC functionality can be maintained when the system is powered
off. The AD8195 meets all the requirements for sink tests as
defined in Section 8 of the HDMI Compliance Test 1.3c.
The AD8195 is specified to operate over the −40°C to +85°C
temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
PARALLEL
VTTI
CONTROL
LOGIC
AD8195
AVCC
AMUXVCC
AVEE
VTTO
IP[3:0]
IN[3:0]
+
VREF_IN
44
4 EQ BUFFER PE 4
HIGH SPEED BUFFERED
+ OP[3:0]
ON[3:0]
VREF_OUT
SCL_IN
SDA_IN
22
SCL_OUT
SDA_OUT
CEC_IN
LOW SPEED BUFFERED
BIDIRECTIONAL
Figure 1.
CEC_OUT
TYPICAL APPLICATION
MEDIA CENTER
SET-TOP BOX
DVD PLAYER
HDMI
RECEIVER
4:1 HDMI
SWITCH
HDTV SET
AD8195
GAME
CONSOLE
BACK PANEL
CONNECTORS
FRONT PANEL
CONNECTOR
Figure 2. Typical AD8195 Application for HDTV Sets
PRODUCT HIGHLIGHTS
1. Enables a fully HDMI 1.3a-compliant front panel input.
2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
3. Input cable equalizer enables use of long cables; more than
20 meters (24 AWG) at data rates of up to 2.25 Gbps.
4. Auxiliary buffer isolates and buffers the DDC bus and CEC
line for a single chip, fully HDMI 1.3a-compliant solution.
5. Auxiliary buffer is powered independently from the TMDS
link so that DDC/CEC functionality can be maintained
when the system is powered off.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.



Analog Devices AD8195
AD8195* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
AD8195 Evaluation Board
DOCUMENTATION
Data Sheet
AD8195: HDMI/DVI Buffer with Equalization Data Sheet
REFERENCE MATERIALS
Informational
• Advantiv™ Advanced TV Solutions
Technical Articles
Analysis of Common Failures of HDMI CT
DESIGN RESOURCES
AD8195 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
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Analog Devices AD8195
AD8195
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application........................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
TMDS Performance Specifications ............................................ 3
Auxiliary Channel Performance Specifications........................ 4
Power Supply and Control Logic Specifications ...................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
REVISION HISTORY
8/12—Rev. A to Rev. B
Changed Data Rate = 3 Gbps to
Data Rate = 2.25 Gbps .................................................. Throughout
Changes to Features Section, General Description Section, and
Product Highlights Section ............................................................. 1
Changes to Table 1............................................................................ 3
Changes to specifications statements in Typical Performance
Characteristics Section..................................................................... 8
Changes to Figure 19...................................................................... 11
Changes to Theory of Operation Section and to
Input Channels Section.................................................................. 13
Changes to Output Channels Section.......................................... 13
Changes to Preemphasis Section .................................................. 14
Changes to Cable Lengths and Equalization Section and
PCB Layout Guidelines Section.................................................... 16
Added Unused DDC/CEC Buffers Section................................. 18
Data Sheet
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 13
Input Channels ........................................................................... 13
Output Channels ........................................................................ 13
Preemphasis ................................................................................ 14
Auxiliary Lines............................................................................ 14
Applications Information .............................................................. 15
Front Panel Buffer for Advanced TV....................................... 15
Cable Lengths and Equalization............................................... 16
TMDS Output Rise/Fall Times................................................. 16
PCB Layout Guidelines.............................................................. 16
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
8/11—Rev. 0 to Rev. A
Changed Data Rate = 2.25 Gbps to
Data Rate = 2.25 Gbps .................................................. Throughout
Changes to Features Section, General Description Section, and
Product Highlights Section ..............................................................1
Changes to Table 1.............................................................................3
Changes to Table 3.............................................................................4
Changes to Figure 5 Caption and Figure 7 Caption .....................8
Added Figure 6 and Figure 8; Renumbered Sequentially ............8
Moved Figure 9 and Figure 11 .........................................................9
Changes to Figure 9 Caption and Figure 11 Caption ...................9
Added Figure 10 and Figure 12 .......................................................9
Moved Figure 14 and Figure 16 .................................................... 10
Changes to Figure 14 Caption and Figure 16 Caption .............. 10
Added Figure 15 and Figure 17 .................................................... 10
Changes to Figure 18, Figure 19, and Figure 21 ......................... 11
Changes to Input Channels Section............................................. 13
Changes to Output Channels Section.......................................... 13
Changes to Preemphasis Section.................................................. 14
Changes to Cable Lengths and Equalization Section, TMDS
Output Rise/Fall Times Section, and PCB Layout Guidelines
Section.............................................................................................. 16
Changes to Auxiliary Control Signals Section ........................... 18
8/08—Revision 0: Initial Version
Rev. B | Page 2 of 20







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