Signal Processor. ADDI7015 Datasheet

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ADDI7015 Datasheet
Recommendation ADDI7015 Datasheet
Part ADDI7015
Description 16-Bit CCD Signal Processor
Feature ADDI7015; Data Sheet Quad-Channel, 16-Bit CCD Signal Processor with Precision Timing Core ADDI7015 FEATURES .
Manufacture Analog Devices
Datasheet
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Analog Devices ADDI7015
Data Sheet
Quad-Channel, 16-Bit CCD Signal
Processor with Precision Timing Core
ADDI7015
FEATURES
4 independent AFE channels
1.8 V analog and digital core supply voltage
Complete on-chip ISATG timing generator with 16 XV
outputs and 4 general-purpose outputs (GPO)
Differential analog inputs
CDS or SHA (CDS bypass) with 7 gain settings
0 dB to 36 dB, 10-bit variable gain amplifier (VGA)
16-bit, 65 MSPS analog-to-digital converter (ADC)
Precision Timing core with 240 ps resolution at 65 MHz
8 programmable H-clock outputs
On-chip sync generator with external sync input
8 mm × 8 mm CSP_BGA package with 0.65 pitch
APPLICATIONS
Industrial cameras
Surveillance cameras
Medical imaging
Professional photography
GENERAL DESCRIPTION
The ADDI7015 is a highly integrated, quad-channel, CCD
signal processor for high speed digital imaging applications.
Each channel is specified at pixel rates of up to 65 MHz and
consists of a complete analog front end (AFE) with analog-to-
digital conversion. The Precision Timing® core allows adjust-
ment of the correlated double sampler (CDS) and sample-and-
hold amplifier (SHA) clocks with 240 ps resolution at 65 MHz
operation. There are eight independent horizontal clock outputs
to support a variety of CCD timing requirements. The
ADDI7015 also features a programmable ISATG for vertical
timing generation.
Each analog front end includes black level clamping, a CDS, a
VGA, and a 65 MSPS, 16-bit analog-to-digital converter (ADC).
Operation is programmed using a 4-wire serial interface.
Packaged in a space-saving, 8 mm × 8 mm, CSP_BGA, the
ADDI7015 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ADDI7015
INP_A
INM_A
CDS/
SHA
0dB TO 18dB
AFE_A
VGA
0dB TO 36dB
VREF
ADC
CLAMP
INP_B
INM_B
INP_C
INM_C
INP_D
INM_D
H1 TO H8
8
XV1 TO XV16
16
ISATG
GPO1 TO GPO4
4
AFE_B
AFE_C
AFE_D
INTERNAL CLOCKS
Precision
Timing
CORE
SYNC
GENERATOR
REDUCED
RANGE
LVDS
INTERFACE
INTERNAL
REGISTERS
DOUT0P_A
DOUT0N_A
DOUT1P_A
DOUT1N_A
DOUT0P_B
DOUT0N_B
DOUT1P_B
DOUT1N_B
TCLKP_AC
TCLKN_AC
TCLKP_BD
TCLKN_BD
DOUT0P_C
DOUT0N_C
DOUT1P_C
DOUT1N_C
DOUT0P_D
DOUT0N_D
DOUT1P_D
DOUT1N_D
CLI
HD VD SYNC
NOTES
1. THE CIRCUITRY FOR AFE_A TO AFE_D IS IDENTICAL.
Figure 1.
SL1 SL2 SDATA SCK
For more information on the ADDI7015, email Analog Devices, Inc., at afe.ccd@analog.
Rev. Sp0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.



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DOCUMENTATION
Data Sheet
ADDI7015: Quad-Channel, 16-Bit CCD Signal Processor
with Precision Timing Core Data Sheet
DESIGN RESOURCES
ADDI7015 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
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Analog Devices ADDI7015
ADDI7015
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10869F-0-8/12(Sp0)
Rev. Sp0 | Page 2 of 2







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