Audio Amplifier. SSM4321 Datasheet

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SSM4321 Datasheet
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Part SSM4321
Description Mono 2.9 W Class-D Audio Amplifier
Feature SSM4321; Data Sheet Mono 2.9 W Class-D Audio Amplifier with Digital Current and Voltage Output SSM4321 FEAT.
Manufacture Analog Devices
Datasheet
Download SSM4321 Datasheet




Analog Devices SSM4321
Data Sheet
Mono 2.9 W Class-D Audio Amplifier
with Digital Current and Voltage Output
SSM4321
FEATURES
Filterless Class-D amplifier with spread-spectrum
Σ-Δ modulation
Digitized output of output voltage, output current,
and PVDD supply voltage
72 dB signal-to-noise ratio (SNR) on output current sensing
and 77 dB SNR on output voltage sensing
TDM or multichip I2S slave output interface
Up to 4 chips supported on a single bus
8 kHz to 48 kHz operation
I2S/left justified slave output interface
1 or 2 chips supported on a single bus
8 kHz to 48 kHz operation
PDM output interface operates from 1 MHz to 6.144 MHz
2.2 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion plus noise (THD + N)
89% efficiency at 5.0 V, 1.4 W into 8 Ω + 0.2 Ω RSENSE speaker
>100 dB signal-to-noise ratio (SNR)
High PSRR at 217 Hz: 86 dB
Amplifier supply operation from 2.5 V to 5.5 V
Input/output supply operation from 1.42 V to 3.6 V
Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps
with fixed input impedance of 80 kΩ
<1 μA shutdown current
Smart power-down with loss of BCLK
Short-circuit and thermal protection with autorecovery
Available in a 16-ball, 0.4 mm pitch, 1.74 mm × 1.74 mm WLCSP
Pop-and-click suppression
APPLICATIONS
Mobile phones
MP3 players
Portable electronics
GENERAL DESCRIPTION
The SSM4321 is a fully integrated, high efficiency, Class-D
audio amplifier with digitized output of output voltage, output
current, and the PVDD supply voltage. It is designed to maximize
performance for mobile phone applications. The application circuit
requires a minimum of external components and operates from
a 2.5 V to 5.5 V supply for the amplifier and a 1.42 V to 3.6 V
supply for input/output. The SSM4321 is capable of delivering
2.2 W of continuous output power with <1% THD + N driving
a 4 Ω load from a 5.0 V supply with a 0.1 Ω V/I sense resistor.
The SSM4321 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modulation
scheme provides high efficiency even at low output power. The
SSM4321 operates with 89% efficiency at 1.4 W into 8 Ω from
a 5.0 V supply with an SNR of >100 dB.
The SSM4321 includes circuitry to sense output current, output
voltage, and the PVDD supply voltage. Current sense is performed
using an external sense resistor that is connected between an
output pin and the load. The output current and voltage are sent
to ADCs with 16-bit resolution; the PVDD supply voltage is sent
to an ADC with 8-bit resolution.
The outputs of these ADCs are available on the TDM or I2S
output serial port. The SLOT pin is used to determine which of
four possible output slots is used on the TDM interface. A stereo
I2S interface can be selected by reversing the pin connections for
BCLK and FSYNC. Also, a direct PDM bit stream of voltage and
current data can be selected via the SLOT pin.
Spread-spectrum pulse density modulation (PDM) is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures. The inherent randomized nature of
spread-spectrum PDM eliminates the clock intermodulation
(beating effect) of several amplifiers in close proximity.
The SSM4321 produces ultralow EMI emissions that significantly
reduce the radiated emissions at the Class-D outputs, particularly
above 100 MHz. The ultralow EMI emissions of the SSM4321 are
also helpful for antenna and RF sensitivity problems.
The device includes a highly flexible gain select pin that requires
only one series resistor to select a gain setting of 0 dB, 3 dB, 6 dB,
9 dB, or 12 dB. Input impedance is fixed at 80 kΩ, independent
of the selected gain.
The SSM4321 has a shutdown mode with a typical shutdown
current of <1 μA. Shutdown is enabled by removing the BCLK
input. A clock must be present on the BCLK pin for the part
to operate.
The device also includes pop-and-click suppression circuitry,
which minimizes voltage glitches at the output during turn-on
and turn-off, reducing audible noise on activation and deactivation.
The SSM4321 is specified over the industrial temperature range
of −40C to +85C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a halide-free, 16-ball,
0.4 mm pitch, 1.74 mm × 1.74 mm wafer level chip scale package
(WLCSP).
Rev. 0
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Analog Devices SSM4321
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EVALUATION KITS
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SSM4321 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DOCUMENTATION
Data Sheet
SSM4321: Mono 2.9 W Class-D Audio Amplifier Data Sheet
User Guides
UG-552: Evaluation Board for SSM4321 Class-D Audio
Amplifier with Voltage and Current Sense
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Analog Devices SSM4321
SSM4321
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Digital Input/Output Specifications........................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
Overview...................................................................................... 14
Power-Down Operation ............................................................ 14
Gain Selection ............................................................................. 14
Pop-and-Click Suppression....................................................... 14
Output Modulation Description .............................................. 14
EMI Noise.................................................................................... 15
REVISION HISTORY
10/12—Revision 0: Initial Version
Data Sheet
Output Current Sensing ............................................................ 15
Output Voltage Sensing ............................................................. 15
PVDD Sensing ............................................................................ 15
Serial Data Input/Output............................................................... 16
TDM Operating Mode .............................................................. 16
I2S and Left Justified Operating Mode .................................... 16
Multichip I2S Operating Mode ................................................. 17
PDM Output Mode .................................................................... 17
Timing Diagrams, TDM Mode ................................................ 18
Timing Diagrams, I2S and Left Justified Modes..................... 18
Timing Diagrams, Multichip I2S Mode ................................... 19
Timing Diagrams, PDM Mode................................................. 20
Applications Information .............................................................. 21
Layout .......................................................................................... 21
Input Capacitor Selection.......................................................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
Rev. 0 | Page 2 of 24







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