LCD Driver. NJU6532 Datasheet

NJU6532 Driver. Datasheet pdf. Equivalent

NJU6532 Datasheet
Recommendation NJU6532 Datasheet
Part NJU6532
Description LCD Driver
Feature NJU6532; 1/3, 1/4 Duty LCD Driver NJU6532 Preliminary GENERAL DESCRIPTION NJU6532 is a 1/3 or 1/4 duty segm.
Manufacture New Japan Radio
Datasheet
Download NJU6532 Datasheet




New Japan Radio NJU6532
1/3, 1/4 Duty LCD Driver
NJU6532
Preliminary
GENERAL DESCRIPTION
NJU6532 is a 1/3 or 1/4 duty segment type LCD driver.
It incorporates 4 common driver circuits and 32 segment driver
circuits. NJU6532 can drive maximum 96(84)* segments in
1/3 duty ratio and maximum 128(112)* segments in 1/4 duty
ratio.
Be addition, the NJU6532's useful functions and small
package meet a wide range of applications.
PACKAGE OUTLINE
NJU6532FR3 NJU6532V
FEATURES
LCD driving circuit
:Max. 32outputs (SSOP44: Max. 28outputs) (4 outputs as for general purpose ports)
Programmable Duty Ratio
1/3 duty ratio
:Driving max. 96 segments (SSOP44:Driving max. 84 segments)
1/4 duty ratio
:Driving max. 128 segments (SSOP44:Driving max. 112 segments)
Programmable Bias Ratio :1/2, 1/3 bias ratio
Serial Data Transfer
:Shift clock max. 2MHz
Built-in Oscillator
:CR oscillation with external resistor, or external oscillation signal input
Display OFF
:INHb terminal
Operating Voltage
:2.7 to 5.5V
LCD Driving Voltage
:Vdd to 8.0V
C-MOS Technology
:P-Sub
Package Outline
:SSOP44, LQFP48-R3
BLOCK DIAGRAM
Excluding SSOP44
COM1 COM4 SEG1
SEG24 SEG25 SEG28 SEG29
SEG32/P4
VDD
VLCD
V1
V2
VSS
INHb
COM
Drivers
Segment Drivers /General Purpose Output Ports
Data Latch Circuit
OSC1
OSC2
CSb
SCK
SI
RSTb
Oscillator
Decoder
Display Data Register
Command Register
Ver.2013-01-22
-1-



New Japan Radio NJU6532
NJU6532
PIN CONFIGURATION
LQFP48-R3
Preliminary
VLCD
V1
V2
VSS
INHb
RSTb
CSb
SI
SCK
VDD
OSC1
OSC2
37
38
39
40
41
42
43
44
45
46
47
48
NJU6532
24 SEG20
23 SEG19
22 SEG18
21 SEG17
20 SEG16
19 SEG15
18 SEG14
17 SEG13
16 SEG12
15 SEG11
14 SEG10
13 SEG9
SSOP44
44 23
NJU6532
1 22
-2-
Ver.2013-01-22



New Japan Radio NJU6532
NJU6532
TERMINAL DISCRIPTION
Preliminary
No. Terminal Function
LQFP48-R3 SSOP44
46 36
VDD Power supply: 3V /5V
37
27
VLCD
LCD driving voltage
VLCD V1 V2 VSS, VLCD VDD
38, 28,
39 29
V1,
V2
Bias
At 1/3 bias ratio, keep V1- V2 open.
At 1/2 bias ratio, short V1- V2.
40 30
VSS
GND
VSS =0V
Display OFF *
When INHb is "H", display is ON, and when INHb is "L", display is off.
41 31 INHb
When SEG29(P1)~SEG32 (P4) are selected as general purpose output
ports, even if input “0” to INHb terminal, SEG29~32 will still be
recognized as general purpose output ports.
42
32
RSTb
Reset
When RSTb is “L", command register and latch circuit is reset.
43
33
CSb
Chip select
When CSb is "L", data can be read in.
44 34
SI Serial data input (8 bit=1word)
45 35 SCK Serial clock
External resistor connection terminal for CR oscillation, or external
47, 37, OSC1, clock input terminal
48 38 OSC2 When external clock is used, input the signal to OSC1 and keep OSC2
open.
1~4
39~42
COM1 ~ Common driver outputs
COM4
5~28
43~44
1~22
SEG1 ~ Segment driver outputs
SEG24
29~32
-
SEG25 ~ Segment driver outputs (Excluding SSOP44)
SEG28
Segment driver outputs/general purpose output ports
33~36
23~26
SEG29/P1
~
SEG32/P4
These 4 terminals can be used as segment outputs or general purpose
output ports by setting Command Register.
When selected as general purpose ports, data can be outputted via these
ports during COM1 timing.
According to transferred data, "H"=VDD or "L"=VSS will be outputted.
*: For details about INHb, please refer to "7 FUNCTION DESCRIPTION (5) Display OFF function (INHb terminal)".
Ver.2013-01-22
-3-







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