SPDT Switches. ADG5233 Datasheet

ADG5233 Switches. Datasheet pdf. Equivalent

ADG5233 Datasheet
Recommendation ADG5233 Datasheet
Part ADG5233
Description Triple/Quad SPDT Switches
Feature ADG5233; Data Sheet FEATURES Latch-up proof 2.8 pF off source capacitance 9 pF off drain capacitance 0.4 pC c.
Manufacture Analog Devices
Datasheet
Download ADG5233 Datasheet




Analog Devices ADG5233
Data Sheet
FEATURES
Latch-up proof
2.8 pF off source capacitance
9 pF off drain capacitance
0.4 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
Human body model (HBM) ESD rating
8 kV input/output port to supplies
2 kV input/output port to input/output port
8 kV all other pins
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5233 and ADG5234 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double throw (SPDT) switches and four indepen-
dently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG5233 (LFCSP and TSSOP packages) is used to
enable or disable the device. When disabled, all channels are
switched off.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
High Voltage Latch-Up Proof,
Triple/Quad SPDT Switches
ADG5233/ADG5234
FUNCTIONAL BLOCK DIAGRAMS
ADG5233
S1A
D1
S1B
S2B
D2
S2A
S3B
D3
S3A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 1. ADG5233 TSSOP and LFCSP_WQ
ADG5234
S1A
D1
S1B
IN1
S4A
D4
S4B
IN4
IN2
S2B
D2
S2A
IN3
S3B
D3
S3A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 2. ADG5234 TSSOP and LFCSP_WQ
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
2. Ultralow Capacitance and 0.4 pC Charge Injection.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5233/ADG5234 can be operated from dual supplies
up to ±22 V.
4. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5233/ADG5234 can be operated from a single-rail
power supply up to 40 V.
5. 3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
6. No VL Logic Power Supply Required.
Rev. D
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Analog Devices ADG5233
ADG5233/ADG5234
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
REVISION HISTORY
8/15—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4............................................................................ 6
Changes to Table 7............................................................................ 9
Changes to Figure 20 Caption to Figure 22 Caption ................. 14
Changes to Figure 23 Caption to Figure 25 Caption ................. 15
Deleted Figure 20 and Figure 22; Renumbered Sequentially ... 15
Deleted Figure 24, Figure 26, and Figure 28 ............................... 16
Deleted Figure 30............................................................................ 17
12/14—Rev. B to Rev. C
Changes to Features Section and Product Highlights Section ... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 7
Change to Table 7 ............................................................................. 9
Changes to Figure 7 to Figure 12.................................................. 13
Changes to Figure 13 and Figure 14............................................. 14
Changes to Figure 19, Figure 20 Caption, and
Figure 22 Caption .......................................................................... 15
Added Figure 21 and Figure 23; Renumbered Sequentially ..... 15
Changes to Figure 24 Caption, Figure 26 Caption, and
Figure 28 Caption ........................................................................... 16
Added Figure 25, Figure 27, and Figure 28................................. 16
Changes Figure 30 Caption ........................................................... 17
Added Figure 31.............................................................................. 17
Changes to Figure 34...................................................................... 18
Data Sheet
Continuous Current per Channel, Sx or Dx..............................7
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 16
Terminology .................................................................................... 18
Trench Isolation.............................................................................. 19
Applications Information .............................................................. 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
6/13—Rev. A to Rev. B
Added 20-Lead LFCSP ......................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
3/12—Rev. 0 to Rev. A
Added 16-Lead LFCSP ......................................................Universal
Changes to Ordering Guide .......................................................... 22
7/11—Revision 0: Initial Version
Rev. D | Page 2 of 22



Analog Devices ADG5233
Data Sheet
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C −40°C to +85°C −40°C to +125°C
VDD to VSS
160
Unit
V
Ω typ
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
200 250
3.5
89
38
50 65
±0.02
280
10
70
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Drain Off Leakage, ID (Off )
±0.1 ±0.2
±0.02
±0.4
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
±0.1
±0.08
±0.2
±0.2
±0.3
0.002
3
125
160 190
145
175 210
125
155 170
45
0.4
±0.4
±0.9
2.0
0.8
±0.1
215
240
180
25
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−76
dB typ
Channel-to-Channel Crosstalk
−87
dB typ
−3 dB Bandwidth
355
MHz typ
Insertion Loss
−6.4
dB typ
CS (Off )
CD (Off )
CD (On), CS (On)
2.8
9
13
pF typ
pF typ
pF typ
Rev. D | Page 3 of 22
ADG5233/ADG5234
Test Conditions/Comments
VS = ±10 V, IS = −1 mA;
see Figure 28
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = 10 V;
see Figure 30
VS = ±10 V, VD = 10 V;
see Figure 30
VS = VD = ±10 V; see Figure 26
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 34
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 29
RL = 50 Ω, CL = 5 pF;
see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz





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