ADGS1412

Data Sheet SPI Interface, 1.5 Ω RON, ±15 V/+12 V, Quad SPST Switch, Mux Configurable ADGS1412 FEATURES SPI interface with error detection Includes CRC, invalid read/write address, and SCLK count error detection Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interface compatible Guaranteed break-before-make switching allowing external wiring of switches to deliver multiplexer configurations 1.5 Ω typical on resistance at 25°C 0.3 Ω typical on resistance flatness at 25°C 0.1 Ω typical on resistance match between channels at 25°C VSS to VDD analog signal range Fully specified at ±15 V, ±5 V, and +12 V 1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V 24-lead LFCSP APPLICATIONS Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GENERAL DESCRIPTION The ADGS1412 contains four independent single-pole/singlethrow (SPST) switches. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features such as cyclic redundancy check (CRC) error detection, invalid read/write address detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS1412 devices together. Daisy-chain mode enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS1412 can also operate in burst mode to decrease the time between SPI commands. iCMOS ...