Programmable System-on-Chip. CY8C21512 Datasheet

CY8C21512 System-on-Chip. Datasheet pdf. Equivalent

CY8C21512 Datasheet
Recommendation CY8C21512 Datasheet
Part CY8C21512
Description Automotive Extended Programmable System-on-Chip
Feature CY8C21512; .
Manufacture Cypress Semiconductor
Datasheet
Download CY8C21512 Datasheet




Cypress Semiconductor CY8C21512
CY8C21312
CY8C21512
Automotive PSoC®
Programmable System-on-Chip™
Automotive PSoC® Programmable System-on-Chip™
Features
Automotive Electronics Council (AEC) Q100 qualified
Powerful Harvard-architecture processor
M8C processor speeds up to 24 MHz
Low power at high speed
Operating voltage: 3.0 V to 5.25 V
Automotive temperature range: –40 C to +85 C
Advanced peripherals
One CapSense® block:
• Provides configurable capacitive sensing elements
• Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
One limited digital PSoC® block provides:
• 8-bit timer, counter, or pulse-width modulator (PWM)
• Half-duplex UART
• SPI slave
• Connectable to all general purpose I/O (GPIO) pins
Flexible on-chip memory
8 KB flash program storage
512 bytes SRAM data storage
In-system serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Complete development tools
Free development software (PSoC Designer™)
Full-featured in-circuit emulator (ICE) and programmer
Full-speed emulation
Complex breakpoint structure
128 KB trace memory
Precision, programmable clocking
Internal ±5% 24 MHz oscillator
Internal low-speed, low-power oscillator for Watchdog and
Sleep functionality
Optional external oscillator, up to 24 MHz
Programmable pin configurations
25 mA sink, 10 mA drive on all GPIOs
Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
Analog input on all GPIOs
Configurable interrupt on all GPIOs
Versatile analog mux
Common internal analog bus
Simultaneous connection of I/O combinations
Additional system resources
Inter-Integrated Circuit (I2C™) master, slave, or multi-master
operation up to 400 kHz
Watchdog and sleep timers
User-configurable low-voltage detection (LVD)
Integrated supervisory circuit
On-chip precision voltage reference
Logic Block Diagram
PSoC CORE
Port 3 Port 2 Port 1 Port 0
System Bus
Global Digital
Interconnect
SRAM
512B
Interrupt
Controller
Global Analog Interconnect
SROM Flash 8K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block
ANALOG SYSTEM
Analog Input
Muxing
CapSense Block
Digital
Resources
Analog
Resources
Digital
Clocks
POR and LVD
I2C
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-63745 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 28, 2018



Cypress Semiconductor CY8C21512
CY8C21312
CY8C21512
Contents
PSoC Functional Overview .............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
20-Pin Part Pinout ....................................................... 8
28-Pin Part Pinout ....................................................... 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 14
Operating Temperature ............................................. 14
DC Electrical Characteristics ..................................... 15
AC Electrical Characteristics ..................................... 18
Packaging Information ................................................... 23
Packaging Diagram ................................................... 23
Thermal Impedances ................................................. 24
Solder Reflow Specifications ..................................... 24
Tape and Reel Information ........................................ 25
Development Tool Selection ......................................... 27
Software .................................................................... 27
Development Kits ...................................................... 27
Evaluation Tools ........................................................ 27
Device Programmers ................................................. 28
Accessories (Emulation and Programming) .............. 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Acronyms ........................................................................ 30
Reference Documents .................................................... 30
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Numeric Conventions .................................................... 31
Glossary .......................................................................... 31
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC® Solutions ...................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Document Number: 001-63745 Rev. *F
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Cypress Semiconductor CY8C21512
CY8C21312
CY8C21512
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional microcontroller unit (MCU)-based system
components with one, low-cost single-chip programmable
component. A PSoC device includes configurable blocks of
analog and digital logic, and programmable interconnect. This
architecture makes it possible for you to create customized
peripheral configurations, to match the requirements of each
individual application. Additionally, a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts.
The PSoC architecture, as illustrated in the Logic Block Diagram
on page 1, comprises of four main areas: the core, the system
resources, the digital system, and the analog system.
Configurable global bus resources allow all the device resources
to be combined into a complete custom system. Each
CY8C21x12 device includes one limited digital block and one
CapSense block. Depending on the PSoC package, up to 24
GPIOs are also included. The GPIOs provide access to the
global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers, and an internal
main oscillator (IMO) and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System Resources provide additional capability, such as digital
clocks for increased flexibility, I2C functionality for implementing
an I2C master, slave, or multi-master, an internal voltage
reference that provides an absolute value of 1.3 V to a number
of PSoC subsystems, and various system resets supported by
the M8C.
The Digital System is composed of a programmable limited
digital block and fixed-function digital resources inside the
CapSense block. The limited digital block can be configured into
a number of digital peripherals. The fixed-function digital
resources in the CapSense block provide external modulation
signals, measurement timing, and measurement conversion.
The digital resources can be connected to the GPIO through a
series of global buses that provide very flexible routing options.
The Analog System is composed of a comparator and a filter that
are used in the CapSense block to implement capacitive sensing
measurement.
The Digital System
The Digital System is composed of one digital block. This block
is an 8-bit resource that can implement various 8-bit digital
peripherals. Digital peripheral configurations include those listed.
PWM (8-bit)
Counter (8-bit)
Timer (8-bit)
Half-duplex 8-bit UART with selectable parity
SPI slave
I2C master, slave, or multi-master (implemented in a dedicated
I2C block)
The digital block can be connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
8
8
DIGITAL SYSTEM
LDB0
Digital Array
Row 0
CapSense0
4
Analog Digital
3
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
8
8
Document Number: 001-63745 Rev. *F
Page 3 of 38







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