CapSense Controller. CY8C21634B Datasheet

CY8C21634B Controller. Datasheet pdf. Equivalent

CY8C21634B Datasheet
Recommendation CY8C21634B Datasheet
Part CY8C21634B
Description Programmable System-on-Chip CapSense Controller
Feature CY8C21634B; CY8C21x34B PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21.
Manufacture Cypress Semiconductor
Datasheet
Download CY8C21634B Datasheet




Cypress Semiconductor CY8C21634B
CY8C21x34B
CPaSpoSCe®nsPer®ogCraomntmroallbelrewSityhstSemma-ortnS-eCnhsipe™™
Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
Features
Advanced CapSense® block with SmartSense™ Auto-Tuning
Patented CSD sensing algorithm
SmartSense_EMC Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
Driven shield
Delivers best-in class water tolerant designs
Robust proximity sensing in the presence of metal objects
Supports longer trace lengths
Powerful Harvard-architecture processor
M8C processor speeds up to 24 MHz
Low power at high speed
Operating voltage: 2.4 V to 5.25 V
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
Industrial temperature range: -40 °C to 85 °C
Advanced peripherals (PSoC® blocks)
Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART), serial peripheral interface (SPI) master or slave
• Connectable to all general purpose I/O (GPIO) pins
Implement a combination up to 21 buttons or 4 sliders using
4 analog blocks and 3 digital blocks
Complex peripherals by combining blocks
Flexible on-chip memory
8-KB Flash /512-B SRAM
50,000 erase/write cycles
In-system serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Complete development tools
Free development software (PSoC Designer™)
Full-featured, in-circuit emulator (ICE) and programmer
Full-speed emulation
Complex breakpoint structure
128-KB trace memory
Precision, programmable clocking
Internal ±2.5% 24- / 48-MHz main oscillator[1]
Internal oscillator for watchdog and sleep
Programmable pin configurations
25-mA sink, 10-mA source on all GPIOs
Pull-up, pull-down, high-Z, strong, or open-drain drive modes
on all GPIOs
Up to eight analog inputs on GPIOs
Configurable interrupt on all GPIOs
Versatile analog mux
Common internal analog bus
Simultaneous connection of I/O combinations
Capacitive sensing application capability
Additional system resources
I2C[2] master, slave, and multi-master to 400 kHz
Watchdog and sleep timers
User-configurable low-voltage detection (LVD)
Integrated supervisory circuit
On-chip precision voltage reference
Package options
16-pin SOIC
20-pin, 28-pin, 56-pin SSOP
32-pin QFN
Errata: For information on silicon errata, see “Errata” on page 48. Details include trigger conditions, devices affected, and proposed workaround.
Notes
1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.
2. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep
mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-67345 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 3, 2018



Cypress Semiconductor CY8C21634B
Logic Block Diagram
CY8C21x34B
Document Number: 001-67345 Rev. *H
Page 2 of 52



Cypress Semiconductor CY8C21634B
CY8C21x34B
More Information
Cypress provides a wealth of data at www.cypress.com to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article “How to Design with PSoC® 1,
PowerPSoC®, and PLC – KBA88292”. Following is an
abbreviated list for PSoC 1:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Designer includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
Getting Started with PSoC® 1 – AN75320.
PSoC® 1 - Getting Started with GPIO – AN2094.
PSoC® 1 Analog Structure and Configuration – AN74170.
PSoC® 1 Switched Capacitor Analog Blocks – AN2041.
Selecting Analog Ground and Reference – AN2219.
Note: For CY8C21x34B devices related Application note please
click here.
Development Kits:
CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
CY3214-PSoCEvalUSB features a development board for
the CY8C24x94 PSoC device. Special features of the board
include USB and CapSense development and debugging
support.
Note: For CY8C21x34B devices related Development Kits
please click here.
The MiniProg1 and MiniProg3 devices provide interfaces for
flash programming and debug.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code. Figure 1 shows PSoC Designer windows. Note: This is not
the default view.
1. Global Resources – all device hardware settings.
2. Parameters – the parameters of the currently selected User
Modules.
3. Pinout – information related to device pins.
4. Chip-Level Editor – a diagram of the resources available on
the selected chip.
5. Datasheet – the datasheet for the currently selected UM
6. User Modules – all available User Modules for the selected
device.
7. Device Resource Meter – device resource usage for the
current project configuration.
8. Workspace – a tree level diagram of files associated with the
project.
9. Output – output from project build and debug operations.
Note: For detailed information on PSoC Designer, go to
PSoC® Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide.
Figure 1. PSoC Designer Layout
Document Number: 001-67345 Rev. *H
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