Clock Buffer. CY7B993V Datasheet

CY7B993V Buffer. Datasheet pdf. Equivalent

CY7B993V Datasheet
Recommendation CY7B993V Datasheet
Part CY7B993V
Description High-Speed Multi-Phase PLL Clock Buffer
Feature CY7B993V; RoboClock,,™ CY7B994V PRELIMINARY CY7B993V High-Speed Multi-Phase PLL Clock Buffer Features Fun.
Manufacture Cypress Semiconductor
Datasheet
Download CY7B993V Datasheet




Cypress Semiconductor CY7B993V
CY7B993V/CY7B994V
RoboClock®
High-Speed Multi-Phase PLL Clock Buffer
High-Speed Multi-Phase PLL Clock Buffer
Features
500 ps Max Total Timing Budget (TTB™) window
12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz
(CY7B994V) Input/Output Operation
Matched Pair Output Skew < 200 ps
Zero Input-to-Output Delay
18 LVTTL Outputs Driving 50Terminated Lines
16 Outputs at 200 MHz: Commercial Temperature
6 Outputs at 200 MHz: Industrial Temperature
3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable
Reference Inputs
Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
Multiply/Divide Ratios of 1–6, 8, 10, 12
Individual Output Bank Disable
Output High Impedance Option for Testing Purposes
Fully Integrated Phase Locked Loop (PLL) with Lock Indicator
<50-ps Typical Cycle-to-Cycle Jitter
Single 3.3V ± 10% Supply
100-pin TQFP Package
100-pin BGA Package
Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated
transmission lines with impedances as low as 50while delivering
minimal and specified output skews at LVTTL levels. The outputs are
arranged in five banks. Banks 1 to 4 of four outputs allow a divide
function of 1 to 12, while simultaneously allowing phase
adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One
of the output banks also includes an independent clock invert
function. The feedback bank consists of two outputs, which
allows divide-by functionality from 1 to 12 and limited phase
adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change-over to secondary clock source, when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07127 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 27, 2017



Cypress Semiconductor CY7B993V
CY7B993V/CY7B994V
RoboClock®
Logic Block Diagram
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
FBF0
Feedback Bank FBDS0
FBDS1
FBDIS
Bank 4
4F0
4F1
4DS0
4DS1
DIS4
Bank 3
Bank 2
3F0
3F1
3DS0
3DS1
DIS3
INV3
2F0
2F1
2DS0
2DS1
DIS2
Bank 1
1F0
1F1
1DS0
1DS1
DIS1
Phase
Freq.
Detector
Filter
FS
OUTPUT_MODE
3
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
Divide and
Phase
Select
Matrix
VCO
LOCK
Control Logic
Divide and Phase
Generator
QFA0
QFA1
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Document Number: 38-07127 Rev. *O
Page 2 of 23



Cypress Semiconductor CY7B993V
CY7B993V/CY7B994V
RoboClock®
Contents
Pinouts .............................................................................. 4
Pin Definition .................................................................... 6
Block Diagram Description .............................................. 7
Phase Frequency Detector and Filter .......................... 7
VCO, Control Logic, Divider,
and Phase Generator ......................................................... 7
Time Unit Definition ..................................................... 7
Divide and Phase Select Matrix .................................. 8
Output Disable Description .......................................... 9
INV3 Pin Function ..................................................... 10
Lock Detect Output Description ................................. 10
Factory Test Mode Description ................................. 10
Safe Operating Zone ................................................. 10
Absolute Maximum Conditions ..................................... 11
Operating Range ............................................................. 11
Electrical Characteristics ............................................... 11
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
AC Timing Diagrams ...................................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-07127 Rev. *O
Page 3 of 23







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