Delay Buffer. CY23FS04 Datasheet

CY23FS04 Buffer. Datasheet pdf. Equivalent

CY23FS04 Datasheet
Recommendation CY23FS04 Datasheet
Part CY23FS04
Description 2.5V / 3.3V Zero Delay Buffer
Feature CY23FS04; CY23FS04 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Features ■.
Manufacture Cypress Semiconductor
Datasheet
Download CY23FS04 Datasheet





Cypress Semiconductor CY23FS04
CY23FS04
Failsafe™ 2.5 V/3.3 V Zero Delay Buffer
Failsafe™ 2.5 V/3.3 V Zero Delay Buffer
Features
Internal digital controlled crystal oscillator (DCXO) for
continuous glitch-free operation
Zero input-output propagation delay
Low jitter (35 ps max RMS) outputs
Low output-to-output skew (200 ps max)
4.17 MHz to 166.7 MHz reference input
Supports industry standard input crystals
166.7 MHz outputs
5 V tolerant Inputs
Phase-locked loop (PLL) bypass mode
Dual reference inputs
16-Pin thin shrunk small outline package (TSSOP)
2.5 V or 3.3 V output power supplies
3.3 V core power supply
Industrial temperature range
Logic Block Diagram
XIN XOUT
REFSEL
DCXO
Functional Description
The CY23FS04 is a FailSafezero delay buffer with two
reference clock inputs and four phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
The continuous, glitch-free operation is achieved by using a
DCXO. This serves as a redundant clock source in the event of
a reference clock failure by maintaining the last frequency and
phase information of the reference clock.
The unique feature of the CY23FS04 is that the DCXO is the
primary clocking source, which is synchronized (phase-aligned)
to the external reference clock. When this external clock is
restored, the DCXO automatically resynchronizes to the external
clock.
The frequency of the crystal that is connected to the DCXO must
be an integer factor of the frequency of the reference clock. This
factor is set by two select lines: S[2:1], see Configuration Table
on page 3. The output power supply VDD can be connected to
either 2.5 V or 3.3 V. VDDC is the power supply pin for internal
circuits and must be connected to 3.3 V.
For a complete list of related documentation, click here.
REF1
REF2
FBK
FailsafeTM
Block
S[2:1]
Decoder
2
PLL
2
CLKA[2:1]
2 CLKB[2:1]
FAIL# /SAFE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07304 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 14, 2017



Cypress Semiconductor CY23FS04
CY23FS04
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Configuration Table .......................................................... 3
FailSafe Function .............................................................. 4
XTAL Selection Criteria and Application Example ........ 6
Absolute Maximum Conditions ....................................... 8
Recommended Pullable Crystal Specifications ............ 8
Operating Conditions ....................................................... 9
Electrical Characteristics ................................................. 9
Thermal Resistance .......................................................... 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC®Solutions ....................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 38-07304 Rev. *M
Page 2 of 16



Cypress Semiconductor CY23FS04
CY23FS04
Pin Configuration
Figure 1. 16-pin TSSOP pinout
CY23FS04
REF1
REF2
CLKB1
CLKB2
S2
VSS
VDDC
XIN
1
2
3
4
5
6
7
8
16 REFSEL
15 FBK
14 CLKA1
13 CLKA2
12 S1
11 VDD
10 FAIL#/SAFE
9 XOUT
16 pin TSSOP
Pin Definitions
Pin No.
2, 1
4, 3
13, 14
15
5, 12
8
9
10
11
7
6
16
Pin Name
REF[2:1]
CLKB[2:1]
CLKA[2:1]
FBK
S[2:1]
XIN
XOUT
FAIL#/SAFE
VDD
VDDC
VSS
REFSEL
Description
Reference clock inputs. 5 V tolerant.[4]
Bank B clock outputs.[1,2]
Bank A clock outputs.[1,2]
Feedback input to the PLL.[1,4]
Frequency select pins and PLL and DCXO bypass mode.[3]
Reference crystal input.
Reference crystal output.
Valid reference indicator. A high level indicates a valid reference input.
2.5 V or 3.3 V power supply.
3.3 V power supply.
Ground.
Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1
is selected; REFSEL = 0, REF2 is selected.
Configuration Table
S[2:1]
00
01
10
11
XTAL (MHz)
Min Max
8.33 30.00
8.00 25.00
8.33 27.78
REF (MHz)
Min Max
4.17
16.00
50.00
15.00
50.00
166.70
OUT (MHz)
Min Max
REF:OUT
Ratio
PLL and DCXO Bypass Mode
4.17 15.00
x1
16.00 50.00
x1
50.00 166.70
x1
REF:XTAL
Ratio
1/2
2
6
Out:XTAL
Ratio
1/2
2
6
Notes
1. For normal operation, connect either one of the four clock outputs to the FBK input.
2. Weak pull-downs on all outputs.
3. Weak pull-ups on these inputs.
4. Weak pull-down on these inputs
Document Number: 38-07304 Rev. *M
Page 3 of 16





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