Fanout Buffer. CY2CP1504 Datasheet

CY2CP1504 Buffer. Datasheet pdf. Equivalent

CY2CP1504 Datasheet
Recommendation CY2CP1504 Datasheet
Part CY2CP1504
Description 1:4 LVCMOS to LVPECL Fanout Buffer
Feature CY2CP1504; CY2CP1504 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input 1:4 LVCMOS to LVPECL Fanou.
Manufacture Cypress Semiconductor
Datasheet
Download CY2CP1504 Datasheet




Cypress Semiconductor CY2CP1504
CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Features
Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 250 MHz operation
Synchronous clock enable function
20-Pin thin shrunk small outline package (TSSOP) package
2.5-V or 3.3-V operating voltage [1]
Commercial and industrial operating temperature range
Functional Description
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
For a complete list of related documentation, click here.
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-56313 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 13, 2016



Cypress Semiconductor CY2CP1504
CY2CP1504
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Absolute Maximum Ratings ............................................4
Operating Conditions .......................................................4
DC Electrical Specifications ............................................5
Thermal Resistance ..........................................................5
AC Electrical Specifications ............................................6
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC®Solutions ........................................................14
Cypress Developer Community .................................14
Technical Support ......................................................14
Document Number: 001-56313 Rev. *J
Page 2 of 14



Cypress Semiconductor CY2CP1504
Pin Configurations
Figure 1. 20-pin TSSOP Package pinout
CY2CP1504
Pin Definitions
Pin No.
1
2
Pin Name
VSS
CLK_EN
3 IN_SEL
4
5, 7, 8, 9
6
10, 13, 18
11, 14, 16, 19
12, 15, 17, 20
IN0
NC
IN1
VDD
Q(0:3)#
Q(0:3)
Pin Type
Power
Input
Input
Input
Input
Power
Output
Output
Description
Ground
Synchronous clock enable. LVCMOS/low-voltage transistor-transistor logic (LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, input IN0 is active
When IN_SEL = High, input IN1 is active
LVCMOS input clock. Active when IN_SEL = Low
No connection
LVCMOS input clock. Active when IN_SEL = High
Power supply
LVPECL complementary output clocks
LVPECL output clocks
Document Number: 001-56313 Rev. *J
Page 3 of 14







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