Clock Generator. CY2544 Datasheet

CY2544 Generator. Datasheet pdf. Equivalent

CY2544 Datasheet
Recommendation CY2544 Datasheet
Part CY2544
Description Quad PLL Programmable Clock Generator
Feature CY2544; CY2544 CY2546 CY2548 Quad PLL Programmable Clock Generator with Spread Spectrum Quad PLL Programmab.
Manufacture Cypress Semiconductor
Datasheet
Download CY2544 Datasheet




Cypress Semiconductor CY2544
CY2544/CY2546/CY2548
Quad-PLL Programmable Clock Generator
with Spread Spectrum
Quad-PLL Programmable Clock Generator with Spread Spectrum
Features
Four fully-integrated phase-locked loops (PLLs)
Input frequency range
External crystal: 8 to 48 MHz for CY2544 and CY2546
External reference: 8 to 166 MHz clock
Reference clock input voltage range
2.5 V, 3.0 V, and 3.3 V for CY2548
1.8 V for CY2544 and CY2546
Wide operating output frequency range
3 to 166 MHz
Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
VDD supply voltage options:
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
1.8 V for CY2546
Selectable output clock voltages:
1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
1.8 V for CY2546
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Power down, output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with Fractional-N
capability
Up to nine clock outputs with programmable drive strength
Glitch free outputs while frequency switching
24-pin QFN package
Commercial and Industrial temperature ranges
One-time programmability
For programming support, contact Cypress technical support
or send an e-mail to clocks@cypress.com
Benefits
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using spread
spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of Zero PPM frequency synthesis error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low-power systems
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
CLKIN
XIN/
EXCLKIN
XOUT
OSC
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL1
PLL2
PLL3
(SS)
Crossbar
Switch
Output
Bank
1
Dividers
and Bank
2
Drive
Strength
Control Bank
3
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
SSON
PLL4
(SS)
PD#/OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12563 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 31, 2017



Cypress Semiconductor CY2544
CY2544/CY2546/CY2548
Contents
Device Selection Guide .................................................... 3
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Pinout ................................................................................ 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 5
Four Configurable PLLs .............................................. 5
Input Reference Clocks ............................................... 5
Multiple Power Supplies .............................................. 6
Output Bank Settings .................................................. 6
Output Source Selection ............................................. 6
Spread Spectrum Control ............................................ 6
Frequency Select ........................................................ 6
Glitch-Free Frequency Switch ..................................... 6
PD#/OE Mode ............................................................. 6
Output Drive Strength .................................................. 6
Generic Configuration and Custom Frequency ........... 6
Output Driver Supply
and Multi-Function Input Restriction ................................... 6
Absolute Maximum Conditions ....................................... 7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................ 7
AC Electrical Specifications ............................................ 9
Configuration Example for C-C Jitter ............................. 9
Recommended Crystal Specification ............................. 9
Recommended Crystal Specification ........................... 10
Test and Measurement Setup ........................................ 10
Voltage and Timing Definitions ..................................... 10
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definitions ......................................... 12
Package Drawing and Dimensions ............................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-12563 Rev. *M
Page 2 of 17



Cypress Semiconductor CY2544
CY2544/CY2546/CY2548
Device Selection Guide
Device
CY2544
CY2546
CY2548
Crystal Input
Yes
EXCKLKIN Input
1.8 V LVCMOS
CLKIN Input
VDD
VDD_CLK_BX
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 1.8 V, 2.5 V, 3.0 V, 3.3 V
Yes 1.8 V LVCMOS
1.8 V LVCMOS
1.8 V
1.8 V
No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 1.8 V, 2.5 V, 3.0 V, 3.3 V
Pinout
Figure 1. 24-pin QFN pinout
CY2544 / CY2548
24 23 22 21 20 19
GND 1
18 GND
CLK1 2
VDD_CLK_B1 3
PD#OE 4
CY2544
24LD QFN
17 CLK8
16 VDD_CLK_B3
15 CLK7/SSON
NC 5
14 VDD_CLK_B2
CLK2 6
13 CLK6
7 8 9 10 11 12
24 23 22 21 20 19
GND 1
18 GND
CLK1 2
VDD_CLK_B1 3
PD#OE 4
CY2548
24LD QFN
17 CLK8
16 VDD_CLK_B3
15 CLK7/SSON
NC 5
14 VDD_CLK_B2
CLK2 6
13 CLK6
7 8 9 10 11 12
Pin Definitions
CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number Name
I/O
Description
1
GND
Power Power supply ground
2
CLK1
Output Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
3
VDD_CLK_B1
Power Power supply for Bank1, (CLK1, CLK2, CLK3) Outputs: 1.8 V/2.5 V/3.0 V/3.3 V
4
PD#/OE
Input Multifunction programmable pin. Output enable or power-down mode
5 NC NC No Connect
6
CLK2
Output Programmable clock output with spread spectrum. Output voltage depends on
VDD_CLK_B1 voltage
7
GND
Power Power supply ground
8 CLK3/FS0 Output/input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
9
OE/FS1
Input Multifunction programmable pin. Output enable or frequency select pin
10 CLK4/FS2 Output/input Multifunction programmable pin. Programmable clock output with no spread spectrum
or frequency select input pin. Output voltage of CLK4 depends on VDD_CLK_B2 voltage
Document Number: 001-12563 Rev. *M
Page 3 of 17







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