Storage Controller. CYWB0163BB Datasheet

CYWB0163BB Controller. Datasheet pdf. Equivalent

CYWB0163BB Datasheet
Recommendation CYWB0163BB Datasheet
Part CYWB0163BB
Description USB and Mass Storage Controller
Feature CYWB0163BB; CYWB0163BB/CYWB0164BB West Bridge® Bay™ USB and Mass Storage Controller Features ■ Best-in-class si.
Manufacture Cypress Semiconductor
Datasheet
Download CYWB0163BB Datasheet




Cypress Semiconductor CYWB0163BB
CYWB0163BB/CYWB0164BB
West Bridge® Bay™ USB and Mass
Storage Controller
Features
Best-in-class sideloading performance (>30 MBps) based on
Cypress's proprietary SLIM® II technology, enabling direct path
from Hi-Speed USB 2.0 to mass storage devices
USB-IF compliance certified
USB 2.0 peripheral
High-Speed On-The-Go (HS-OTG) 2.0 host negotiation pro-
tocol (HNP) and session request protocol (SRP)
Thirty-two endpoints
Integrated USB 2.0 transceivers
EZ-Dtect™ – USB charger detection 1.1
Accessory charger adaptor (ACA)
Integrated Hi-Speed USB 2.0 switch[1]
Carkit Pass-Through UART functionality on USB
Mass storage support
SD 3.0 (SDXC) UHS-1
eMMC 4.4
System I/O expansion with two secure digital I/O (SDIO) ports
Native mass storage class (MSC), human interface device
(HID), full, and Turbo-MTPTM support
Flexible host processor interface
Asynchronous non-multiplexed SRAM
Synchronous and asynchronous address/data multiplexed
SRAM
Multimedia card (MMC) slave with eMMC 4.3/4.4
pass-through boot
Direct memory access (DMA) slave support over processor
interfaces
Ultra low-power in core power-down mode
Less than 60 µA with VBATT on and 20 µA with VBATT off
Independent and flexible power domains
Flexible serial peripheral interfaces (SPIs)
I2C master controller at 1 MHz
I2S master (transmitter only) with sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
UART at 4 Mbps
SPI master at 33 MHz
Selectable clocking frequencies
19.2-, 26-, 38.4-, and 52-MHz clock input
19.2-MHz crystal input
32-kHz low-power clock for watchdog timer
Package options:
5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
Pin compatible with West Bridge® Benicia™ enabling easy
migration to USB 3.0
Applications
Mobile phones
Portable media players
Portable navigation devices
Personal digital assistant devices
Digital still/video cameras
Note
1. Available only with the WLCSP package.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-45550 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 21, 2014



Cypress Semiconductor CYWB0163BB
CYWB0163BB/CYWB0164BB
Logic Block Diagram
PMMC
P
P
ADMUX
Async
O
R
T
ADMUX
Sync
SRAM
Async
ARM9
Embedded
SRAM
HS/FS/LS
OTG Host
32 HS/FS
EPs Peripheral
U
P
O
R
T
EZ-Dtect™
HS [2]
USB
Switch
UART
SPI
I2C I2S
SD/MMC Controller
S0-PORT
S1-PORT
Note
2. Available only with the WLCSP package.
Document Number: 001-45550 Rev. *J
Page 2 of 52



Cypress Semiconductor CYWB0163BB
CYWB0163BB/CYWB0164BB
Contents
Functional Overview ........................................................ 4
Interface Description ........................................................ 4
USB Interface (U-Port) ................................................ 4
Storage Port (S-Port) ................................................... 8
Host Processor Interface (P-Port) ............................... 8
Other Interfaces ......................................................... 10
Boot Options ................................................................... 11
Reset ................................................................................ 11
Hard Reset ................................................................ 11
Soft Reset .................................................................. 11
Clocking .......................................................................... 11
32-kHz Watchdog Timer Clock Input ......................... 12
Power ............................................................................... 12
Power Modes ............................................................ 13
Configuration Options ................................................... 15
EMI ................................................................................... 15
System-level ESD ........................................................... 15
Pin Description ............................................................... 16
Absolute Maximum Ratings .......................................... 26
Operating Conditions ..................................................... 26
DC Specifications ........................................................... 26
AC Timing Parameters ................................................... 28
Storage Port Timing .................................................. 28
Host Processor Interface (P-Port) Timing ................. 31
Low Performance Peripherals Timing ....................... 38
SPI Timing Specification ........................................... 41
Reset Sequence .............................................................. 42
Package Diagram ............................................................ 44
Ordering Information ...................................................... 46
Ordering Code Definitions ......................................... 46
Acronyms ........................................................................ 47
Document Conventions ................................................. 47
Units of Measure ....................................................... 47
Errata ............................................................................... 48
Part Numbers Affected .............................................. 48
Bay and Benicia, USB and
Mass Storage Peripheral Controller Qualification Status . 48
Bay and Benicia, USB and
Mass Storage Peripheral Controller Errata Summary ...... 48
Document History Page ................................................. 50
Sales, Solutions, and Legal Information ...................... 52
Worldwide Sales and Design Support ....................... 52
Products .................................................................... 52
PSoC® Solutions ...................................................... 52
Cypress Developer Community ................................. 52
Technical Support ..................................................... 52
Document Number: 001-45550 Rev. *J
Page 3 of 52







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