Peripheral Controller. CYWB0321ABX-FDXI Datasheet

CYWB0321ABX-FDXI Controller. Datasheet pdf. Equivalent

CYWB0321ABX-FDXI Datasheet
Recommendation CYWB0321ABX-FDXI Datasheet
Part CYWB0321ABX-FDXI
Description Arroyo USB and Mass Storage Peripheral Controller
Feature CYWB0321ABX-FDXI; CYWB0320ABX-FDXI CYWB0321ABX-FDXI West Bridge®: Arroyo USB and Mass Storage Peripheral Controller W.
Manufacture Cypress Semiconductor
Datasheet
Download CYWB0321ABX-FDXI Datasheet




Cypress Semiconductor CYWB0321ABX-FDXI
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
West Bridge®: Arroyo USB and
Mass Storage Peripheral Controller
West Bridge®: Arroyo USB and Mass Storage Peripheral Controller
Features
Multimedia device support
Support next-gen SD, SDHC, SDIO, and MMC+
Simultaneous link to independent multimedia (SLIM®)
architecture, enabling simultaneous and independent data
paths between the processor and USB, and between the USB
and mass storage.
High speed USB at 480 Mbps
USB 2.0 compliant
Integrated USB 2.0 transceiver, smart Serial Interface Engine
16 programmable endpoints
Flexible processor interface, which supports:
SPI (slave mode) interface
Multiplexing and nonmultiplexing address and data interface
SRAM interface
Pseudo CRAM interface
Pseudo NAND Flash interface
DMA slave support
Logic Block Diagram
Ultra low power, 1.8 V core operation
Low power modes
Small footprint, 3.9 × 3.9 mm, 0.4 mm pitch, WLCSP
Supports USB Boot, I2C Boot and Processor Boot
Clock input frequency
19.2 MHz
26 MHz
Applications
Cellular phones
Portable media players
Personal digital assistants
Portable navigation devices
Digital cameras
POS terminals
Portable video recorders
Control Registers
µC
Access Control
P
SLIM™
Mass Storage Interface
SD/MMC
S
U
Errata: For information on silicon errata, see “Errata” on page 50 and “Errata” on page 51. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57458 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 1, 2014



Cypress Semiconductor CYWB0321ABX-FDXI
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Contents
Functional Overview ........................................................ 3
The SLIM Architecture ................................................. 3
8051 Microprocessor ................................................... 3
Configuration and Status Registers ............................. 3
Processor Interface (P-Port) ........................................ 3
USB Interface (U-Port) ................................................ 3
Clocking ....................................................................... 3
Power Domains ........................................................... 4
Power Modes .............................................................. 5
Pin Assignments .............................................................. 6
Absolute Maximum Ratings .......................................... 13
Operating Conditions ..................................................... 13
DC Characteristics ......................................................... 14
AC Timing Parameters ................................................... 16
P Port Interface ......................................................... 16
S Port Interface AC Timing Parameters .................... 43
Reset and Standby Timing Parameters .................... 45
Ordering Information ...................................................... 47
Ordering Code Definitions ......................................... 47
Package Diagram ............................................................ 48
Acronyms ........................................................................ 49
Document Conventions ................................................. 49
Units of Measure ....................................................... 49
Errata ............................................................................... 50
Part Numbers Affected .............................................. 50
Arroyo Qualification Status ........................................ 50
Arroyo Errata Summary ............................................. 50
Errata ............................................................................... 51
Part Numbers Affected .............................................. 51
Arroyo Qualification Status ........................................ 51
Arroyo Errata Summary ............................................. 51
Document History Page ................................................. 52
Sales, Solutions, and Legal Information ...................... 54
Worldwide Sales and Design Support ....................... 54
Products .................................................................... 54
PSoC® Solutions ...................................................... 54
Cypress Developer Community ................................. 54
Technical Support ..................................................... 54
Document Number: 001-57458 Rev. *H
Page 2 of 54



Cypress Semiconductor CYWB0321ABX-FDXI
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Functional Overview
The SLIM Architecture
The SLIM architecture enables three different interfaces (P-port,
S-port, and U-port) to connect to each other independently.
With this architecture, a device using Arroyo is connected to a
PC through a USB, without disturbing any of the device
functions. The device can still access mass storage when the PC
is synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
PC accesses a mass storage device independent of the main
processor, or enumerates access to both the mass storage and
the main processor at the same time.
You can do the following in a handset using SLIM architecture:
Use the phone as a thumb drive.
Download media files to the phone with all the functionalities
still available on the phone.
Use the same phone as a modem to connect the PC to the
internet.
8051 Microprocessor
The 8051 microprocessor embedded in Arroyo does basic
transaction management for all transactions between the P-Port,
S-Port, and the U-Port. The 8051 does not reside in the data
path; it manages the path. The data path is optimized for
performance. The 8051 executes firmware that supports SD,
SDHC, SDIO, and MMC+ devices at the S-Port.
Configuration and Status Registers
The West Bridge® Arroyo device includes configuration and
status registers that are accessible as memory-mapped
registers through the processor interface. The configuration
registers enable the system to specify some behaviors of Arroyo.
For example, it can mask certain status registers from raising an
interrupt. The status registers convey the status of Arroyo, such
as the addresses of buffers for read operations.
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface also can be configured to a
pseudo NAND interface to support the processor’s NAND
interface. In addition, this interface can be configured to support
SPI slave. Asynchronous accesses can reach a bandwidth of up
to 66.7 MBps. Synchronous accesses can be performed at
33 MHz across 16 bits for up to 66.7 MBps bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Arroyo. These endpoints serve as buffers
for data between each pair of ports; for example, between the
processor port and the USB port. The processor writes and reads
to these buffers through the memory interface.
Access to these buffers is controlled by using a DMA protocol or
using an interrupt to the main processor. These two modes are
configured by the external processor.
As a DMA slave, Arroyo generates a DMA request signal to notify
the main processor that a specific buffer is ready to be read from
or written to. The external processor monitors this signal and
polls Arroyo for the specific buffers ready for a read or write
operation. It then performs the appropriate read or write
operations on the buffer through the processor interface. As a
result, the external processor only deals with the buffers to
access a storage device connected to Arroyo.
In the Interrupt mode, Arroyo communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Arroyo for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations through the processor interface.
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Arroyo can
operate in both full speed and high speed USB modes. The USB
interface consists of the USB transceiver. The USB interface can
access and be accessed by both the P-Port and the S-Port.
The Arroyo USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Mass Storage Support (S-Port)
The S-Port may be configured to support the following:
Next-gen SD/SDIO/eMMC+ port
When Arroyo is configured through firmware to support
SD/SDIO/MMC+, this interface supports the following:
SD Memory Card Specification - Part 1, Physical Layer
Specification, SD Group, Version 2.0, May 9, 2006.
SD Memory Card Specification - Part 1, Physical Layer
Specification, SD Group, Version 1.10, October 15, 2004.
SD Specifications - Part E1 SDIO specification, Version 1.10,
August 18, 2004.
The Multimedia Card System Specification, MMCA Technical
Committee, Version 4.1.
West Bridge Arroyo supports 1-bit and 4-bit SD and SDIO cards;
1-bit, 4-bit, and 8-bit MMC; MMC+ cards. For the SD, SDIO, and
MMC/MMC Plus, this block supports one card for one physical
bus interface. Arroyo supports SD commands including the
multisector program command that is handled by API
Clocking
Arroyo enables connection of an external clock at the XTALIN
pin. The power supply level at the crystal supply XVDDQ
determines whether a crystal or a clock is provided. If XVDDQ is
detected to be 1.8 V, Arroyo assumes that a clock input is
provided. For a crystal to be connected, XVDDQ must be 3.3 V.
Note Clock inputs at 3.3 V level are not supported.
The 81-pin WLCSP supports 19.2 MHz and 26 MHz external
clock input. The crystal or clock frequency selection is shown in
Table 1 on page 4.
Document Number: 001-57458 Rev. *H
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