Peripheral Controller. CY7C64713 Datasheet

CY7C64713 Controller. Datasheet pdf. Equivalent

CY7C64713 Datasheet
Recommendation CY7C64713 Datasheet
Part CY7C64713
Description Full Speed USB Peripheral Controller
Feature CY7C64713; CY7C64713 EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller EZ-USB FX1™ USB Micr.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C64713 Datasheet




Cypress Semiconductor CY7C64713
CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Features
Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
Fit, form, and function upgradable to the FX2LP (CY7C68013A)
Pin compatible
Object code compatible
Functionally compatible (FX1 functionality is a subset of the
FX2LP)
Draws no more than 65 mA in any mode, making the FX1
suitable for bus powered applications
Software: 8051 runs from internal RAM, which is:
Downloaded using USB
Loaded from EEPROM
External memory device (128 pin configuration only)
16 KB of on-chip code/data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT)
endpoint
64-byte
8- or 16-bit external data interface
Smart media standard ECC generation
GPIF
Allows direct connection to most parallel interfaces; 8- and
16-bit
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple ready (RDY) inputs and Control (CTL)
outputs
Integrated, industry standard 8051 with enhanced features:
Up to 48 MHz clock rate
Four clocks for each instruction cycle
Two USARTS
Three counters or timers
Expanded interrupt system
Two data pointers
3.3 V operation with 5 V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the setup and DATA portions of a
CONTROL transfer
Integrated I2C controller, running at 100 or 400 KHz
48 MHz, 24 MHz, or 12 MHz 8051 operation
Four integrated FIFOs
Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
FIFOs can use externally supplied clock or asynchronous
strobes
Easy interface to ASIC and DSP ICs
Vectored for FIFO and GPIF Interrupts
Up to 40 general purpose IOs (GPIO)
Four package options:
128-pin TQFP
100-pin TQFP
56-pin SSOP
56-pin QFN Pb-free
Errata: For information on silicon errata, see “Errata” on page 71. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-08039 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 9, 2014



Cypress Semiconductor CY7C64713
CY7C64713
Logic Block Diagram
24 MHz
Ext. XTAL
FX1
High performance micro
using standard tools
with lower-power options
/0.5
VCC x20 /1.0
PLL /2.0
1.5k
connected for
enumeration
D+
D–
Integrated
full speed XCVR
USB
XCVR
CY
Smart
USB
Engine
8051 Core
12/24/48 MHz,
four clocks/cycle
16 KB
RAM
Enhanced USB core
Simplifies 8051 code
‘Soft Configuration’
Easy firmware changes
I2C
Master
Additional IOs (24)
ECC
ADDR (9)
GPIF
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Up to 96 MBytes
burst rate
FIFO and endpoint memory
(master or slave operation)
Document Number: 38-08039 Rev. *L
Page 2 of 74



Cypress Semiconductor CY7C64713
CY7C64713
Contents
Functional Description ..................................................... 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
USB Signaling Speed .................................................. 4
8051 Microprocessor ................................................... 4
I2C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 5
ReNumeration™ .......................................................... 6
Bus-powered Applications ........................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 8
Program/Data RAM ..................................................... 9
Endpoint RAM ........................................................... 11
External FIFO Interface ............................................. 11
GPIF .......................................................................... 12
ECC Generation ........................................................ 13
USB Uploads and Downloads ................................... 13
Autopointer Access ................................................... 13
I2C Controller ............................................................. 13
Compatible with Previous Generation
EZ-USB FX2 ..................................................................... 14
Pin Assignments ............................................................ 14
CY7C64713 Pin Definitions ............................................ 20
Register Summary .......................................................... 28
Absolute Maximum Ratings .......................................... 47
Operating Conditions ..................................................... 47
DC Characteristics ......................................................... 47
USB Transceiver ....................................................... 47
AC Electrical Characteristics ........................................ 48
USB Transceiver ....................................................... 48
PORTC Strobe Feature Timings ............................... 51
GPIF Synchronous Signals ....................................... 52
Slave FIFO Synchronous Read ................................. 53
Slave FIFO Asynchronous Read ............................... 54
Slave FIFO Synchronous Write ................................. 55
Slave FIFO Asynchronous Write ............................... 56
Slave FIFO Synchronous Packet End Strobe ........... 56
Slave FIFO Asynchronous Packet End Strobe ......... 58
Slave FIFO Output Enable ........................................ 58
Slave FIFO Address to Flags/Data ............................ 58
Slave FIFO Synchronous Address ............................ 59
Slave FIFO Asynchronous Address .......................... 59
Sequence Diagram .................................................... 60
Ordering Information ...................................................... 64
Ordering Code Definitions ......................................... 64
Package Diagrams .......................................................... 65
Quad Flat Package No Leads (QFN) Package
Design Notes ................................................................... 68
Acronyms ........................................................................ 70
Document Conventions ................................................. 70
Units of Measure ....................................................... 70
Errata ............................................................................... 71
Part Numbers Affected .............................................. 71
EZ-USB FX1 Qualification Status .............................. 71
EZ-USB FX1 Errata Summary .................................. 71
Document History Page ................................................. 72
Sales, Solutions, and Legal Information ...................... 74
Worldwide Sales and Design Support ....................... 74
Products .................................................................... 74
PSoC® Solutions ...................................................... 74
Cypress Developer Community ................................. 74
Technical Support ..................................................... 74
Document Number: 38-08039 Rev. *L
Page 3 of 74







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)