Peripheral Controller. CYUSB3025 Datasheet

CYUSB3025 Controller. Datasheet pdf. Equivalent

CYUSB3025 Datasheet
Recommendation CYUSB3025 Datasheet
Part CYUSB3025
Description USB and Mass Storage Peripheral Controller
Feature CYUSB3025; CYUSB302x SD3™ USB and Mass Storage Peripheral Controller Features ■ Latest-generation storage supp.
Manufacture Cypress Semiconductor
Datasheet
Download CYUSB3025 Datasheet




Cypress Semiconductor CYUSB3025
CYUSB302x
SD3™ USB and Mass Storage
Peripheral Controller
Features
Latest-generation storage support
SD3.0/SDXC – UHS1 SDR50 / DDR50 Master
eMMC 4.4 Master
SDIO 3.0 Master
USB integration
Certified USB 3.0 and USB 2.0 peripheral: SuperSpeed (SS),
Hi-Speed (HS), and Full-Speed (FS) only)
Thirty-two physical endpoints
Integrated transceiver
Accessory charger adaptor (ACA) support
Ultra low-power in core power-down mode
Less than 60 µA with VBATT on and 20 µA with VBATT off
I2C master controller at 1 MHz
Selectable input clock frequencies
19.2, 26, 38.4, and 52 MHz
19.2-MHz crystal input support
Independent power domains for core and I/O
10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
Logic Block Diagram
Applications
USB thumb drives
Card readers
Laptop with SD slots
SD slot in TV/STB
WIFI Dongles
USB SDIO Bridge
Raid on-Chip Controller
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
JTAG
ARM926EJ-S
Embedded
SRAm
(512 kB/
256 KB)
GPIOs
USB
EPs
SS
Peripheral
HS/FS
Peripheral
UART
SPI
I2C I2S
SDIO/SD/MMC Controller
S0-PORT
S1-PORT
SSRX-
SSRX+
SSTX-
SSTX+
D+
D-
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-55190 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 14, 2016



Cypress Semiconductor CYUSB3025
CYUSB302x
Contents
Functional Overview ........................................................ 3
USB Interface (U-Port) ................................................ 3
Mass-Storage Support (S-Port) ................................... 3
I2C Interface ................................................................ 3
UART Interface ............................................................ 3
I2S Interface ................................................................ 3
SPI Interface ................................................................ 3
Boot Options ................................................................ 4
Reset ........................................................................... 4
Clocking ....................................................................... 4
Power .......................................................................... 5
Configuration Fuse ...................................................... 7
Digital I/Os ................................................................... 7
EMI .............................................................................. 7
System Level ESD ...................................................... 7
Pinout for BGA .................................................................. 7
Pin Description for BGA .................................................. 8
Pinout for WLCSP ........................................................... 11
Pin Description for WLCSP ........................................... 12
AC Timing Parameters ................................................... 15
Storage Port Timing .................................................. 15
I2C Interface Timing .................................................. 18
Absolute Maximum Ratings .......................................... 23
Operating Conditions ..................................................... 23
DC Specifications ........................................................... 24
Reset Sequence .............................................................. 26
Package Diagrams .......................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Errata ............................................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-55190 Rev. *J
Page 2 of 32



Cypress Semiconductor CYUSB3025
CYUSB302x
Functional Overview
SD3™ is a USB 3.0 SuperSpeed mass-storage controller
providing the latest SD/MMC support. SD3 complies with the SD
Specification, Version 3.0, and the MMC Specification, Version
4.41.
SD3 offers the following access paths among USB and mass
storage ports:
A USB-port (U-Port) supporting USB 3.0 peripheral
Two mass-storage ports (S0-Port and S1-Port) supporting
mass-storage devices. Following are the possible
configurations for the two mass-storage ports:
SD and MMC
SD and SD
MMC and MMC
SD and SDIO
MMC and SDIO
SDIO and SDIO
Combinations of these accesses can happen independently or
in an interleaved manner.
The SD3 complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0.
USB Interface (U-Port)
SD3 offers the following features:
Supports USB peripheral functionality compliant with the USB
3.0 Specification Revision 1.0 and is backward-compatible with
the USB 2.0 Specification
Supports up to 16 IN and 16 OUT endpoints.
Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device class to optimize mass-storage
access performance.
As a USB peripheral, SD3 supports UAS and Mass Storage
Class (MSC) peripheral classes.
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Figure 1. USB Interface Signals
SD3
VBATT
VBUS
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
Mass-Storage Support (S-Port)
The SD3 storage interface port supports the following
specifications:
SD Specification, Version 3.0
Multimedia Card-System Specification, MMCA Technical
Committee, Version 4.4
SDIO Host controller compliant with SDIO Specification
Version 3.00
I2C Interface
SD3 has an I2C interface compatible with the I2C Bus
Specification Revision 3. Because SD3’s I2C interface is capable
of operating only as I2C master, it may be used to communicate
with other I2C slave devices. For example, SD3 may boot from
an EEPROM connected to the I2C interface, as a selectable boot
option.
SD3’s I2C master controller also supports multi-master mode
functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock stretching
feature to enable slower devices to exercise flow control.
Both SCL and SDA signals of the I2C interface require external
pull-up resistors. These resistors must be connected to VIO5.
UART Interface
The UART interface of SD3 supports full-duplex communication.
It includes the signals noted in Table 1.
Table 1. UART Interface Signals
Signal
TX
RX
CTS
RTS
Description
Output signal
Input signal
Flow control
Flow control
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then SD3's UART only transmits data when the CTS
input is asserted. In addition to this, SD3's UART asserts the RTS
output signal, when it is ready to receive data.
I2S Interface
SD3 has an I2S port to support external audio codec devices.
SD3 functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). SD3 can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
SPI Interface
SD3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 21 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Document Number: 001-55190 Rev. *J
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