Port Controller. CYPD1122 Datasheet

CYPD1122 Controller. Datasheet pdf. Equivalent

CYPD1122 Datasheet
Recommendation CYPD1122 Datasheet
Part CYPD1122
Description USB Type-C Port Controller
Feature CYPD1122; CCG1 Datasheet USB Type-C Port Controller with Power Delivery General Description CCG1 provides a c.
Manufacture Cypress Semiconductor
Datasheet
Download CYPD1122 Datasheet




Cypress Semiconductor CYPD1122
CCG1 Datasheet
USB Type-C Port Controller with
Power Delivery
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support.
Applications
Notebooks, tablets, monitors, docking stations
Power adapters, USB Type-C cables
Features
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Integrated analog blocks
12-bit, 1-Msps ADC for VBUS voltage and current monitoring
Dynamic overcurrent and overvoltage protection
Integrated digital blocks
Two configurable 16-bit TCPWM blocks
One I2C master or slave
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Type-C Support
Integrated transceiver (BB PHY)
Supports up to two USB ports with PD
Supports routing of all protocols through an external mux
PD Support
Supports Provider and Consumer roles
Supports all power profiles
Low-Power Operation
3.2 V to 5.5 V operation
Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
40-pin QFN
16-pin SOIC
35-ball wafer-level CSP (WLCSP)
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-93639 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 3, 2016



Cypress Semiconductor CYPD1122
CCG1 Datasheet
Contents
Functional Definition ........................................................ 3
CPU and Memory Subsystem ..................................... 3
System Resources ...................................................... 3
GPIO ........................................................................... 3
Pin Definitions .................................................................. 4
Pinouts ............................................................................ 10
Power ............................................................................... 11
Electrical Specifications ................................................ 12
Absolute Maximum Ratings ...................................... 12
Device-Level Specifications ...................................... 12
Digital Peripherals ..................................................... 14
Memory ..................................................................... 15
System Resources .................................................... 16
Applications in Detail ..................................................... 18
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Packaging ........................................................................ 24
Acronyms ........................................................................ 27
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Revision History ............................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-93639 Rev. *J
Page 2 of 31



Cypress Semiconductor CYPD1122
CCG1 Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and a Wakeup Interrupt Controller
(WIC). The WIC can wake the processor up from the Deep Sleep
mode, allowing power to be switched off to the main processor
when the chip is in the Deep Sleep mode. The Cortex-M0 CPU
provides a Non-Maskable Interrupt (NMI) input, which is made
available to the user when it is not in use for system functions
requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for CCG1 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The CCG1 device has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash block is designed to deliver 1 wait-state
(WS) access time at 48 MHz and 0-WS access time at 24 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section Power on
page 11. It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The
CCG1 operates with a single external supply over the range of
3.2 V to 5.5 V operation and has three different power modes:
Active, Sleep, and Deep Sleep; transitions between modes are
managed by the power system.
Serial Communication Blocks (SCB)
The CCG1 has one SCB, which can implement an I2C interface.
The hardware I2C block implements a full multi-master and slave
interface (it is capable of multimaster arbitration). This block is
capable of operating at speeds of up to 1 Mbps (Fast Mode Plus)
and has flexible buffering options to reduce interrupt overhead
and latency for the CPU. It also supports EZ-I2C that creates a
mailbox address range in the memory of the CCG1 and effec-
tively reduces I2C communication to reading from and writing to
an array in memory. In addition, the block supports an 8-deep
FIFO for receive and transmit which, by increasing the time given
for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices, as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
The CCG1 is not completely compliant with the I2C spec in the
following respects:
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a
VOL maximum of 0.6 V.
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
When the SCB
between NACK
is an I2C Master, it interposes an
and Repeated Start; the I2C spec
IDLE state
defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
When the SCB is in the I2C Slave mode, and Address Match
on External Clock is enabled (EC_AM = 1) along with operation
in the internally clocked mode (EC_OP = 0), then its I2C
address must be even.
GPIO
The CCG1 has up to 30 GPIOs, which are configured for various
functions. Refer to the pinout tables for the definitions. The GPIO
block implements the following:
Eight drive strength modes:
Analog input mode (input and output buffers disabled)
Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode).
Selectable slew rates for dV/dt related noise control to improve
EMI.
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network, known as a high-speed
I/O matrix, is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 001-93639 Rev. *J
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