Low Voltage. CY7C60323 Datasheet

CY7C60323 Voltage. Datasheet pdf. Equivalent

CY7C60323 Datasheet
Recommendation CY7C60323 Datasheet
Part CY7C60323
Description enCoRe III Low Voltage
Feature CY7C60323; CY7C603xx enCoRe™ III Low Voltage enCoRe™ III Low Voltage Features ■ Powerful Harvard-architecture .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C60323 Datasheet




Cypress Semiconductor CY7C60323
CY7C603xx
enCoRe™ III Low Voltage
enCoRe™ III Low Voltage
Features
Powerful Harvard-architecture processor
M8C processor speeds to 12 MHz
Low power at high speed
2.4 V to 3.6 V operating voltage
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
Commercial temperature range: 0 °C to +70 °C
Configurable peripherals
8-bit timers, counters, and PWM
Full duplex master or slave SPI
10-bit ADC
8-bit successive approximation ADC
Comparator
Flexible on-chip memory
8K flash program storage 50,000 erase/write cycles
512 bytes SRAM data storage
In-System serial programming (ISSP)
Partial flash updates
Flexible protection modes
EEPROM emulation in flash
Complete development tools
Free development software (PSoC® Designer™)
Full-featured, In-circuit emulator and programmer
Complex breakpoint structure
128K trace memory
Precision, programmable clocking
Internal ±2.5% 24 and 48 MHz oscillator
Internal oscillator for watchdog and sleep
Programmable pin configurations
10 mA drive on all general purpose I/O (GPIO)
Pull-up, pull-down, high-Z, strong, or open drain drive modes
on all GPIO
Up to 8 analog inputs on GPIO
Configurable interrupt on all GPIO
Versatile analog mux
Common internal analog bus
Simultaneous connection of IO combinations
Additional system resources
I2C master, slave, and Multimaster to 400 kHz
Watchdog and sleep timers
User-configurable low-voltage detection
Integrated supervisory circuit
On-chip precision voltage reference
Applications
Wireless mice
Wireless gamepads
Wireless presenter tools
Wireless keypads
PlayStation® 2 wired gamepads
PlayStation 2 bridges for wireless gamepads
Applications requiring a cost effective low voltage 8-bit
microcontroller.
Logic Block Diagram
Port 3 Port 2 Port 1 Port 0
System Bus
Global Digital
Interconnect
SRAM
512 Bytes
Interrupt
Controller
Global Analog Interconnect
SROM Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
Clock Sources (Includes IMO and ILO)
enCoRe III LV Core
DIGITAL
SYSTEM
Digital
PSoC
Block
Array
ANALOG SYSTEM
Analog
PSoC
Block
Array
Analog
Ref.
Digital
Clocks
POR and LVD Switch Internal
I2C Mode Voltage
System Resets Pump
Ref.
SYSTEM RESOURCES
Analog
Mux
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-16018 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 23, 2018



Cypress Semiconductor CY7C60323
CY7C603xx
Contents
enCoRe III Low Voltage Functional Overview ................ 3
enCoRe III LV Core ..................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 3
Additional System Resources ..................................... 4
enCoRe III LV Device Characteristics ............................. 4
Getting Started .................................................................. 4
Application Notes ........................................................ 4
Development Kits ........................................................ 4
Training ....................................................................... 4
CYPros Consultants .................................................... 4
Solutions Library .......................................................... 4
Technical Support ....................................................... 4
Development Tools .......................................................... 5
PSoC Designer Software Subsystems ........................ 5
Designing with PSoC Designer ....................................... 6
Select User Modules ................................................... 6
Configure User Modules .............................................. 6
Organize and Connect ................................................ 6
Generate, Verify, and Debug ....................................... 6
Pin Information ................................................................. 7
28-pin Part Pinout ........................................................ 7
32-pin Part Pinout ........................................................ 8
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ....................................... 16
Operating Temperature ............................................. 16
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 22
Packaging Information ................................................... 28
Package Diagrams .................................................... 28
Thermal Impedances ................................................. 29
Solder Reflow Peak Temperature ............................. 29
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Acronyms ........................................................................ 31
Acronyms Used ......................................................... 31
Reference Documents .................................................... 31
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Numeric Conventions .................................................... 32
Glossary .......................................................................... 32
Document History Page ................................................. 37
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41
Document Number: 38-16018 Rev. *Q
Page 2 of 41



Cypress Semiconductor CY7C60323
CY7C603xx
enCoRe III Low Voltage Functional Overview
The enCoRe III low voltage (enCoRe III LV) CY7C603xx device
is based on the flexible PSoC® architecture. This supports a
simple set of peripherals that can be configured to match the
needs of each application. Additionally, a fast CPU, flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. A fast CPU, flash program memory, SRAM
data memory, and configurable IO are included in both 28-pin
SSOP and 32-pin QFN packages.
The enCoRe III LV architecture, as shown in Figure 1, consists
of four main areas: the enCoRe III LV Core, the system
resources, digital system, and analog system. Configurable
global bus resources allow combining all the device resources
into a complete custom system. Each enCoRe III LV device
supports a limited set of digital and analog peripherals.
Depending on the package, up to 28 general purpose I/Os
(GPIOs) are also included. The GPIOs provide access to the
global digital and analog interconnects.
enCoRe III LV Core
The enCoRe III LV core is a powerful engine that supports a rich
feature set. It encompasses SRAM for data storage, an interrupt
controller, sleep and watchdog timers, and IMO (internal main
oscillator) and ILO (internal low-speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a four MIPS 8-bit
Harvard -architecture microprocessor. The core includes a CPU,
memory, clocks, and configurable GPIO.
System resources provide additional capability, such as digital
clocks to increase flexibility, I2C functionality for implementing an
I2C master, slave, multi-master, an internal voltage reference
that provides an absolute value of 1.3 V to a number of
subsystems, a switch mode pump (SMP) that generates normal
operating voltages off a single battery cell, and various system
resets supported by the M8C.
The Digital System
The digital system consists of 4 digital enCoRe III LV blocks.
Each block is an 8-bit resource. Digital peripheral configurations
include the following:
PWM usable as timer or counter
SPI master and slave
I2C slave and multi-master
CMP
ADC10
SARADC
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus To Analog
System
8
8
DIGITAL SYSTEM
Digital enCoRe III LV Block Array
Row 0
4
DBB00
DBB01
DCB02
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
8
8
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The Analog System
The analog system consists of two configurable blocks. Analog
peripherals are very flexible and may be customized to support
specific application requirements. Some of the common analog
functions for this device (available as user modules) are:
Analog-to-digital converters (single with 8-bit resolution)
Pin-to-pin comparators
Single-ended comparators with absolute (1.3-V) reference
1.3-V reference (as a system resource)
Analog blocks are provided in columns of two, which includes
one continuous time (CT) (CT - ACE00 or ACE01) and one
switched capacitor (SC) (SC - ASE10 or ASE11) blocks.
Document Number: 38-16018 Rev. *Q
Page 3 of 41







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