Radio-on-Chip LPstar. CYRF69313 Datasheet

CYRF69313 LPstar. Datasheet pdf. Equivalent

CYRF69313 Datasheet
Recommendation CYRF69313 Datasheet
Part CYRF69313
Description Programmable Radio-on-Chip LPstar
Feature CYRF69313; CYRF69313 Programmable Radio-on-Chip LPstar Programmable Radio-on-Chip LPstar Features ■ Radio Syst.
Manufacture Cypress Semiconductor
Datasheet
Download CYRF69313 Datasheet




Cypress Semiconductor CYRF69313
CYRF69313
Programmable Radio-on-Chip LPstar
Programmable Radio-on-Chip LPstar
Features
Radio System-on-Chip, with built-in 8-bit MCU in a single
device.
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz).
On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP.
Pin-to-pin compatible with PRoC LP except the pin 31 and
pin 37.
Intelligent
M8C based 8-bit CPU, optimized for human interface devices
(HID) applications
256 bytes of SRAM
8 Kbytes of flash memory with EEPROM emulation
In-System reprogrammable through D+/D– pins
CPU speed up to 12 MHz
16-bit free running timer
Low power wakeup timer
12-bit programmable interval timer with interrupts
Watchdog timer
Low Power
21 mA operating current (Transmit at –5 dBm)
Sleep current less than 1 µA
Operating voltage from 4.0 V to 5.25 V DC
Fast startup and fast channel changes
Supports coin-cell operated applications
Reliable and Robust
Receive sensitivity typical –90 dBm
AutoRate™ – dynamic data rate reception
Enables data reception for any of the supported bit rates
automatically.
DSSS (250 Kbps), GFSK (1 Mbps)
Operating temperature from 0 °C to 70 °C
Closed-loop frequency synthesis for minimal frequency drift
Simple Development
Auto transaction sequencer (ATS): MCU can stay sleeping
longer to save power
Framing, length, CRC16, and Auto ACK
Separate 16 byte transmit and receive FIFOs
Receive signal strength indication (RSSI)
Built-in serial peripheral interface (SPI) control while in sleep
mode
Advanced development tools based on Cypress’s PSoC® Tools
Flexible I/O
2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
Each GPIO pin supports high impedance inputs, configurable
pull-up, open-drain output, CMOS/TTL inputs, and CMOS
output
Maskable interrupts on all I/O pins
BOM Savings
Low external component count
Small footprint 40-pin QFN (6 mm × 6 mm)
GPIOs that require no external components
Operates off a single crystal
Integrated 3.3 V regulator
Integrated pull-up on D–
USB Specification Compliance
Conforms to USB specification version 2.0
Conforms to USB HID specification version 1.1
Supports one low speed USB device address
Supports one control endpoint and two data end points
Integrated USB transceiver
Applications
Wireless keyboards and mice
Presentation tools
Wireless gamepads
Remote controls
Toys
Fitness
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66503 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 21, 2014



Cypress Semiconductor CYRF69313
Logic Block Diagram
Vbus
1ohm
CYRF69313
Microcontroller
P0_1,3,4,7
4
P1_6:7
2
Function
P1.5/MOSI
P1.4/SCK
P2_0:1
2
P1.3/nSS
D+/D-
2
RFbias
RFp
Radio
Function
RFn
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
12MHz
.....
.......
Document Number: 001-66503 Rev. *E
Page 2 of 81



Cypress Semiconductor CYRF69313
CYRF69313
Contents
Functional Description ..................................................... 5
Functional Overview ........................................................ 5
2.4 GHz Radio Function .............................................. 5
USB Microcontroller Function ...................................... 5
Backward Compatibility ............................................... 5
Pinouts .............................................................................. 6
Pin Configuration ............................................................. 6
PRoC LPstar Functional Overview ................................. 7
Functional Block Overview .............................................. 8
2.4 GHz Radio ............................................................. 8
Frequency Synthesizer ................................................ 8
Baseband and Framer ................................................. 8
Packet Buffers ............................................................. 9
Auto Transaction Sequencer (ATS) ............................ 9
Interrupts ..................................................................... 9
Clocks .......................................................................... 9
GPIO Interface ............................................................ 9
Power-on Reset ......................................................... 10
Power Management .................................................. 10
Timers ....................................................................... 10
USB Interface ............................................................ 10
Low Noise Amplifier (LNA) and
Received Signal Strength Indication (RSSI) ..................... 10
SPI Interface .................................................................... 10
Three-Wire SPI Interface ........................................... 10
Four-Wire SPI Interface ............................................. 11
SPI Communication and Transactions ...................... 11
SPI I/O Voltage References ...................................... 11
SPI Connects to External Devices ............................ 11
CPU Architecture ............................................................ 12
CPU Registers ................................................................. 13
Flags Register ........................................................... 13
Accumulator Register ................................................ 13
Index Register ........................................................... 13
Stack Pointer Register ............................................... 14
CPU Program Counter High Register ....................... 14
CPU Program Counter Low Register ........................ 14
Addressing Modes ......................................................... 15
Source Immediate ..................................................... 15
Source Direct ............................................................. 15
Source Indexed ......................................................... 15
Destination Direct ...................................................... 15
Destination Indexed ................................................... 16
Destination Direct Source Immediate ........................ 16
Destination Indexed Source Immediate .................... 16
Destination Direct Source Direct ............................... 16
Source Indirect Post Increment ................................. 17
Destination Indirect Post Increment .......................... 17
Instruction Set Summary ............................................... 18
Memory Organization ..................................................... 19
Flash Program Memory Organization ....................... 19
Data Memory Organization ....................................... 20
Flash .......................................................................... 20
SROM ........................................................................ 20
SROM Function Descriptions .................................... 21
Document Number: 001-66503 Rev. *E
SROM Table Read Description ...................................... 24
Clocking .......................................................................... 25
Clock Architecture Description .................................. 26
CPU Clock During Sleep Mode ................................. 32
Reset ................................................................................ 32
Power-on Reset .............................................................. 34
Watchdog Timer Reset .............................................. 34
Sleep Mode ...................................................................... 34
Sleep Sequence ........................................................ 34
Wakeup Sequence .................................................... 35
Low Power in Sleep Mode ......................................... 35
Power-on Reset Control ................................................. 37
POR Compare State ................................................. 37
ECO Trim Register .................................................... 37
General-Purpose I/O Ports ............................................. 38
Port Data Registers ................................................... 38
GPIO Port Configuration ........................................... 39
GPIO Configurations for Low Power Mode ............... 43
Serial Peripheral Interface (SPI) .................................... 44
SPI Data Register ...................................................... 45
SPI Configure Register .............................................. 45
Timer Registers .............................................................. 47
Registers ................................................................... 47
Interrupt Controller ......................................................... 50
Architectural Description ........................................... 50
Interrupt Processing .................................................. 51
Interrupt Latency ....................................................... 51
Interrupt Registers ..................................................... 51
USB Transceiver ............................................................. 56
USB Transceiver Configuration ................................. 56
USB Serial Interface Engine (SIE) ................................. 56
USB Device ..................................................................... 57
Endpoint 0 Mode ....................................................... 58
Endpoint Data Buffers ............................................... 60
USB Mode Tables ........................................................... 61
Mode Column ............................................................ 61
Encoding Column ...................................................... 61
SETUP, IN, and OUT Columns ................................. 61
Details of Mode for Differing Traffic Conditions .......... 62
Register Summary .......................................................... 64
Radio Function Register Descriptions ......................... 66
Absolute Maximum Ratings .......................................... 67
DC Characteristics ......................................................... 67
RF Characteristics .......................................................... 69
AC Test Loads and Waveforms for Digital Pins .......... 70
AC Characteristics ......................................................... 71
Switching Waveforms .................................................... 72
Ordering Information ...................................................... 76
Ordering Code Definitions ......................................... 76
Package Handling ........................................................... 77
Package Diagrams .......................................................... 77
Acronyms ........................................................................ 79
Document Conventions ................................................. 79
Units of Measure ....................................................... 79
Document History Page ................................................. 80
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