Sector Flash. S29AL016J Datasheet

S29AL016J Flash. Datasheet pdf. Equivalent

S29AL016J Datasheet
Recommendation S29AL016J Datasheet
Part S29AL016J
Description Boot Sector Flash
Feature S29AL016J; S29AL016J 16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V, Boot Sector Flash Distinctive Characteristics Arch.
Manufacture Cypress Semiconductor
Datasheet
Download S29AL016J Datasheet




Cypress Semiconductor S29AL016J
S29AL016J
16-Mbit (2M × 8-Bit/1M × 16-Bit), 3 V,
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
Full voltage range: 2.7 to 3.6 volt read and write operations
for battery-powered applications
Manufactured on 110 nm Process Technology
Fully compatible with 200 nm S29AL016D
Secured Silicon Sector region
128-word/256-byte sector for permanent, secure identifica-
tion through an 8-word/16-byte random Electronic Serial
Number accessible through a command sequence
May be programmed and locked at the factory or by the cus-
tomer
Flexible Sector Architecture
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64
Kbyte sectors (byte mode)
One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32
Kword sectors (word mode)
Sector Group Protection Features
A hardware method of locking a sector to prevent any program
or erase operations within that sector
Sectors can be locked in-system or via programming equip-
ment
Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
Reduces overall programming time when issuing multiple
program command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
Pinout and software compatible with single-power supply
Flash
Superior inadvertent write protection
Performance Characteristics
High Performance
Access times as fast as 55 ns
Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Industrial temperature range (–40°C to +85°C)
Extended temperature range (–40°C to +125°C)
Ultra Low Power Consumption (typical values at 5 MHz)
0.2 µA Automatic Sleep mode current
0.2 µA standby mode current
7 mA read current
20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball Fine-pitch BGA
64-ball Fortified BGA
48-pin TSOP
Software Features
CFI (Common Flash Interface) Compliant
Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
Suspends an erase operation to read data from, or program
data to, a sector that is not being erased, then resumes the
erase operation
Data# Polling and Toggle Bits
Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
Provides a hardware method of detecting program or erase
cycle completion
Hardware Reset Pin (RESET#)
Hardware method to reset the device to reading array data
WP# input pin
Fseocrtboor odtespeecntodrindgeovincebso:oattcVoInL,fipgruortaetciotsn
first or last 16 Kbyte
(top boot or bottom
boot)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00777 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 21, 2018



Cypress Semiconductor S29AL016J
S29AL016J
General Description
The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in
48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48-pin TSOP packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with
the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also
be programmed in standard EPROM programmers.
The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AL016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Cypress combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
Document Number: 002-00777 Rev. *Q
Page 2 of 57



Cypress Semiconductor S29AL016J
S29AL016J
Contents
1. Product Selector Guide ............................................... 4
2. Block Diagram.............................................................. 4
3. Connection Diagrams.................................................. 5
3.1 Special Handling Instructions......................................... 7
4. Pin Configuration......................................................... 8
5. Logic Symbol ............................................................... 8
6. Ordering Information ................................................... 9
6.1 S29AL016J Standard Products...................................... 9
6.2 Recommended Combinations...................................... 10
7. Device Bus Operations.............................................. 11
7.1 Word/Byte Configuration.............................................. 12
7.2 Requirements for Reading Array Data......................... 12
7.3 Writing Commands/Command Sequences.................. 12
7.4 Program and Erase Operation Status.......................... 12
7.5 Standby Mode.............................................................. 13
7.6 Automatic Sleep Mode................................................. 13
7.7 RESET#: Hardware Reset Pin..................................... 13
7.8 Output Disable Mode ................................................... 13
7.9 Autoselect Mode .......................................................... 16
7.10 Sector Group Protection/Unprotection ......................... 17
7.11 Temporary Sector Group Unprotect............................. 18
8. Secured Silicon Sector Flash Memory Region ....... 20
8.1 Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory........................................ 20
8.2 Customer Lockable: Secured Silicon Sector NOT
Programmed or Protected at the Factory..................... 21
9. Common Flash Memory Interface (CFI) ................... 22
9.1 Hardware Data Protection............................................ 24
10. Command Definitions................................................ 25
10.1 Reading Array Data ..................................................... 25
10.2 Reset Command .......................................................... 25
10.3 Autoselect Command Sequence ................................. 25
10.4 Enter/Exit Secured Silicon Sector Command
Sequence..................................................................... 26
10.5 Word/Byte Program Command Sequence................... 26
10.6 Unlock Bypass Command Sequence .......................... 26
10.7 Chip Erase Command Sequence ................................ 27
10.8 Sector Erase Command Sequence ............................. 28
10.9 Erase Suspend/Erase Resume Commands ................ 28
10.10Command Definitions Table ......................................... 30
11. Write Operation Status ............................................... 32
11.1 DQ7: Data# Polling ....................................................... 32
11.2 RY/BY#: Ready/Busy#.................................................. 33
11.3 DQ6: Toggle Bit I .......................................................... 33
11.4 DQ2: Toggle Bit II ......................................................... 33
11.5 Reading Toggle Bits DQ6/DQ2..................................... 34
11.6 DQ5: Exceeded Timing Limits ...................................... 35
11.7 DQ3: Sector Erase Timer.............................................. 35
12. Absolute Maximum Ratings....................................... 36
13. Operating Ranges ....................................................... 37
14. DC Characteristics...................................................... 38
14.1 CMOS Compatible ........................................................ 38
15. Test Conditions ........................................................... 39
16. Key to Switching Waveforms..................................... 40
17. AC Characteristics...................................................... 41
17.1 Read Operations........................................................... 41
17.2 Hardware Reset (RESET#)........................................... 42
17.3 Word/Byte Configuration (BYTE#) ................................ 43
17.4 Erase/Program Operations ........................................... 44
17.5 Temporary Sector Group Unprotect.............................. 47
17.6 Alternate CE# Controlled Erase/Program Operations .. 49
18. Erase and Programming Performance ..................... 50
19. TSOP and BGA Pin Capacitance ............................... 50
20. Physical Dimensions .................................................. 51
20.1 TS 048—48-Pin Standard TSOP .................................. 51
20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA)
8.15 mm x 6.15 mm ...................................................... 52
20.3 LAE064—64-Ball Fortified Ball Grid Array (BGA)
9 mm x 9 mm ................................................................ 53
21. Document History ....................................................... 54
Document History Page ..................................................... 54
Sales, Solutions, and Legal Information .......................... 57
Worldwide Sales and Design Support ......................... 57
Products ....................................................................... 57
PSoC® Solutions ......................................................... 57
Cypress Developer Community ................................... 57
Technical Support ........................................................ 57
Document Number: 002-00777 Rev. *Q
Page 3 of 57







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