Sector Flash. S29AS008J Datasheet

S29AS008J Flash. Datasheet pdf. Equivalent

S29AS008J Datasheet
Recommendation S29AS008J Datasheet
Part S29AS008J
Description Boot Sector Flash
Feature S29AS008J; S29AS008J 8 Mbit (1M x 8-Bit / 512K x 16-Bit), 1.8 V Boot Sector Flash Distinctive Characteristics.
Manufacture Cypress Semiconductor
Datasheet
Download S29AS008J Datasheet




Cypress Semiconductor S29AS008J
S29AS008J
8 Mbit (1M x 8-Bit / 512K x 16-Bit), 1.8 V
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– Full voltage range: 1.65 to 1.95 volt read and write operations for
battery-powered applications
Manufactured on 110 nm Process Technology
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence
– May be programmed and locked at the factory or by the customer
Flexible Sector Architecture
– Eight 8 Kbyte and fifteen 64 Kbyte sectors (byte mode)
– Eight 4 Kword, and fifteen 32 Kword sectors (word mode)
Sector Group Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Group Unprotect feature allows code changes
in previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Performance Characteristics
High Performance
– Access times as fast as 70 ns
– Industrial temperature range (-40°C to +85°C)
– Word programming time as fast as 6 µs (typical)
Ultra Low Power Consumption (typical values at 5 MHz)
– 15 µA Automatic Sleep mode current
– 8 µA standby mode current
– 8 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball BGA
48-pin TSOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– Write protect (WP#) function allows protection of two outermost
boot sectors (boot sector models only), regardless of sector group
protect status
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00870 Rev.*J
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 09, 2015



Cypress Semiconductor S29AS008J
S29AS008J
General Description
The S29AS008J is a 8 Mbit, 1.8 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words with a x8/x16 bus and
either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed
and erased in-system with the standard system 1.8 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for program or
erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AS008J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—
an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the
DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to
read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of
other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector group protection feature disables both program and erase operations in any combination of
the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device
enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is
greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Document Number: 002-00870 Rev.*J
Page 2 of 105



Cypress Semiconductor S29AS008J
S29AS008J
Contents
1. Product Selector Guide ............................................... 4
2. Block Diagram.............................................................. 4
3. Connection Diagrams.................................................. 5
3.1 Standard TSOP.............................................................. 5
3.2 FBGA Connection Diagram ........................................... 6
3.3 Special Handling Instructions......................................... 6
4. Pin Configuration......................................................... 7
5. Logic Symbol ............................................................... 7
6. Ordering Information ................................................... 8
6.1 S29AS008J Standard Products ..................................... 8
7. Device Bus Operations................................................ 9
7.1 Word/Byte Configuration................................................ 9
7.2 Requirements for Reading Array Data........................... 9
7.3 Writing Commands/Command Sequences.................. 10
7.4 Program and Erase Operation Status.......................... 10
7.5 Standby Mode.............................................................. 10
7.6 Automatic Sleep Mode................................................. 10
7.7 RESET#: Hardware Reset Pin..................................... 11
7.8 Output Disable Mode ................................................... 11
7.9 Autoselect Mode .......................................................... 11
7.10 Sector Address Tables................................................. 12
7.11 Sector Group Protection/Unprotection ......................... 14
7.12 Temporary Sector Group Unprotect............................. 17
7.13 Write Protect (WP#) ..................................................... 17
7.14 Hardware Data Protection............................................ 18
8. Secured Silicon Sector Flash Memory Region ....... 18
8.1 Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory........................................ 18
8.2 Customer Lockable: Secured Silicon Sector NOT
Programmed or Protected at the Factory ..................... 19
9. Common Flash Memory Interface (CFI) ................... 21
10. Command Definitions................................................ 24
10.1 Reading Array Data ..................................................... 24
10.2 Reset Command .......................................................... 24
10.3 Autoselect Command Sequence ................................. 24
10.4 Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence ................................................... 25
10.5 Word/Byte Program Command Sequence................... 25
10.6 Unlock Bypass Command Sequence .......................... 25
10.7 Chip Erase Command Sequence ................................ 26
10.8 Sector Erase Command Sequence ............................. 27
10.9 Erase Suspend/Erase Resume Commands ................ 27
11. Command Definitions................................................ 29
12. Write Operation Status .............................................. 31
12.1 DQ7: Data# Polling ...................................................... 31
12.2 RY/BY#: Ready/Busy#................................................. 32
12.3 DQ6: Toggle Bit I ......................................................... 33
12.4 DQ2: Toggle Bit II ........................................................ 33
12.5 Reading Toggle Bits DQ6/DQ2.................................... 34
12.6 DQ5: Exceeded Timing Limits ..................................... 35
Document Number: 002-00870 Rev.*J
12.7 DQ3: Sector Erase Timer.............................................. 35
13. Absolute Maximum Ratings....................................... 36
14. Operating Ranges ....................................................... 36
15. DC Characteristics...................................................... 37
15.1 CMOS Compatible ........................................................ 37
16. Test Conditions ........................................................... 38
17. Key to Switching Waveforms..................................... 38
18. AC Characteristics...................................................... 39
18.1 Read Operations........................................................... 39
18.2 Hardware Reset (RESET#)........................................... 40
18.3 Word/Byte Configuration (BYTE#) ................................ 41
18.4 Erase/Program Operations ........................................... 42
18.5 Temporary Sector Group Unprotect.............................. 45
18.6 Alternate CE# Controlled Erase/Program Operations .. 46
19. Erase and Programming Performance ..................... 47
20. Package Pin Capacitance........................................... 48
21. Physical Dimensions .................................................. 49
21.1 TS 048 - 48-Pin Standard TSOP .................................. 49
21.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm ......................................................50
22. Revision History.......................................................... 51
Page 3 of 54







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)